Introduction

The ongoing advance of CMOS based microelectronics is mainly due to the continuous reduction of the device feature size which is expected to decrease for at least another decade [1.1–1.4]. State of the art are gate lengths of 0.13µm, volume production of devices with about 0.10µm gate length is now beginning, and technologies with much shorter gate lengths are under development [1.5]. Additional performance improvements beyond device scaling are obtained by using improved device structures, such as SOI (e.g. [1.6]) or FinFETs (e.g. [1.7]). The introduction of the SiGe technology has opened up new possibilities previously only available in expensive III-V technologies like band-gap engineering and enhancement of carrier mobility by strain [1.8–1.11]. By using strained Si layers pseudomorphically grown on relaxed SiGe layers in the channel region of CMOS devices the performance of MOSFETs has considerably been improved [1.12–1.15]. The performance of Si BJTs has been enhanced by fabricating the base with strained SiGe pseudomorphically grown on the Si bulk [1.16–1.18].