Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Published in:
Cover of the book

2012 | OriginalPaper | Chapter

1. Introduction

Authors : Joachim Haase, Manfred Dietrich

Published in: Process Variations and Probabilistic Integrated Circuit Design

Publisher: Springer New York

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

During the last years, the field of microelectronics has been moving to nanoelectronics. This development provides opportunities for new products and applications. However, development is no longer possible by simply downscaling technical parameters as used in the past. Approaching the physical and technological limits of electronic devices, new effects appear and have to be considered in the design process. Due to the extreme miniaturization in microelectronics, even small variations in the manufacturing process may lead to parameter variations which can make a circuit unusable. A new aspect for digital designers is the occurrence of essential variations not only from die to die but also within a die. Therefore, inter-die and intra-die variations have to be taken into account not only in the design of analog circuits as already done, but also in the digital design process.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
next chapter Physical and Mathematical Fundamentals
Literature
1.
2.
Dennard, R., Gaensslen, F., Rideout, V., Bassous, E., LeBlanc, A.: Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE Journal of Solid-State Circuits 9(5), 256–268 (1974)CrossRef
3.
Meer, P., van Staveren, A.R., M., A.H.: Low-Power Deep Sub-Micron CMOS Logic, 1 edn. Springer (2004)
4.
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2), 305–327 (2003)CrossRef
5.
Bohr, M.: A 30 year retrospective on dennard’s MOSFET scaling paper. IEEE Solid-State Circuits Newsletter 12, 11–13 (2007)CrossRef
6.
Chen, T.C.: Challenges for silicon technology scaling in the nanoscale era. In: Proceedings of the Solid State Device Research Conference, 2009. ESSDERC ’09, pp. 1–7 (2009)
7.
Dennard, B.: (interview) discussing dram and cmos scaling with inventor bob dennard. IEEE Design & Test of Computers 25(2), 188–191 (2008)CrossRef
8.
Mukhopadhyay, S., Roy, K.: Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design ISLPED ’03, pp. 172–175 (2003)
9.
Rabaey, J.: Low Power Design Essentials. Springer, Boston, MA (2009). DOI 10. 1007/978-0-387-71713-5
10.
Srivastava, A., Blaauw, D., Sylvester, D.: Statistical Analysis and Optimization for VLSI: Timing and Power. Springer Science+Business Media Inc, Boston, MA (2005). DOI 10.1007/b137645
11.
Zhao, W., Cao, Y.: New generation of predictive technology model for sub-45 nm early design exploration. IEEE Transactions on Electron Devices 53(11), 2816–2823 (2006)CrossRef
12.
Haselman, M., Hauck, S.: The future of integrated circuits: A survey of nanoelectronics. Proceedings of the IEEE 98(1), 11–38 (2010)CrossRef
13.
Chiang, C.C., Kawa, J.: Design for manufacturability and yield for nano-scale CMOS. Series on integrated circuits and systems. Springer, Dordrecht (2007). DOI 10.1007/ 978-1-4020-5188-3
14.
Kawa, J., Chiang, C., Camposano, R.: EDA challenges in nano-scale technology. In: IEEE Custom Integrated Circuits Conference CICC ’06, pp. 845–851 (2006). DOI 10.1109/CICC.2006.320844
15.
Grabinski, W., Nauwelaers, B., Schreurs, D.e.: Transistor Level Modeling for Analog/RF IC Design, chap. PSP: An Advanced Surface-Potential-Based MOSFET Model, pp. 29–66. Springer, Dordrecht (2006)
16.
Sharma, M., Arora, N.: OPTIMA: A nonlinear model parameter extraction program with statistical confidence region algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12(7), 982–987 (1993)CrossRef
17.
Cheng, B., Dideban, D., Moezi, N., Millar, C., Roy, G., Wang, X., Roy, S., Asenov, A.: Benchmarking statistical compact modeling strategies for capturing device intrinsic parameter fluctuations in BSIM4 and PSP. IEEE Design Test of Computers 27(2), 26–35 (2010). DOI 10.1109/MDT.2010.2CrossRef
18.
Zhao, W., Liu, F., Agarwal, K., Acharyya, D., Nassif, S., Nowka, K., Cao, Y.: Rigorous extraction of process variations for 65-nm CMOS design. IEEE Transactions on Semiconductor Manufacturing 22(1), 196–203 (2009)CrossRef
19.
Orshansky, M., Nassif, S., Boning, D.: Design for Manufacturability and Statistical Design. Springer (2008)
20.
Nassif, S.: Modeling and analysis of manufacturing variations. In: IEEE Conference on Custom Integrated Circuits, pp. 223–228 (2001). DOI 10.1109/CICC.2001.929760
21.
Li, X., Zhao, W., Cao, Y., Zhu, Z., Song, J., Bang, D., Wang, C.C., Kang, S., Wang, J., Nowak, M., Yu, N.: Pathfinding for 22nm CMOS designs using predictive technology models. In: IEEE Custom Integrated Circuits Conference CICC ’09, pp. 227–230 (2009). DOI 10.1109/CICC.2009.5280845
22.
Zhao, W., Li, X., Nowak, M., Cao, Y.: Predictive technology modeling for 32nm low power design. In: 2007 International Semiconductor Device Research Symposium, pp. 1–2 (2007). DOI 10.1109/ISDRS.2007.4422430
23.
Wang, V., Agarwal, K., Nassif, S., Nowka, K., Markovic, D.: A simplified design model for random process variability. IEEE Transactions on Semiconductor Manufacturing 22(1), 12–21 (2009). DOI 10.1109/TSM.2008.2011630CrossRef
24.
Blaauw, D., Chopra, K., Srivastava, A., Scheffer, L.: Statistical timing analysis: From basic principles to state of the art. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(4), 589–607 (2008). DOI 10.1109/TCAD.2007. 907047CrossRef
25.
Graeb, H., Mueller, D., Schlichtmann, U.: Pareto optimization of analog circuits considering variability. In: 18th European Conference on Circuit Theory and Design ECCTD 2007, pp. 28–31 (2007). DOI 10.1109/ECCTD.2007.4529528
Metadata
Title
Introduction
Authors
Joachim Haase
Manfred Dietrich
Copyright Year
2012
Publisher
Springer New York
Book
Process Variations and Probabilistic Integrated Circuit Design

Print ISBN: 978-1-4419-6620-9

Electronic ISBN: 978-1-4419-6621-6

Copyright Year: 2012

DOI
https://doi.org/10.1007/978-1-4419-6621-6_1