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2012 | OriginalPaper | Chapter

1. Introduction

Authors : Qiaoyan Yu, Paul Ampadu

Published in: Transient and Permanent Error Control for Networks-on-Chip

Publisher: Springer New York

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Abstract

Thanks to the rapid advancement of technology in semiconductor device fabrication, billions of transistors can be integrated to a single die [1–5]. Although the increasing chip density potentially facilitates systems-on-chip (SoCs) and chip multiprocessor (CMP) integrating hundreds or thousands of processing element/memory cores, several challenges prevent system further progress, such as design complexity, high-performance interconnect and scalable on-chip communication architecture [6–9]. Networks-on-chip (NoCs) becomes a promising paradigm, which manages the increasing interconnect complexity and facilitates the integration of various intellectual property (IP) cores [10–15].

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next chapter Existing Transient and Permanent Error Management in NoCs

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Title: Introduction
Authors: Qiaoyan Yu
Paul Ampadu
Publisher: Springer New York
Book: Transient and Permanent Error Control for Networks-on-Chip
Print ISBN: 978-1-4614-0961-8

Electronic ISBN: 978-1-4614-0962-5

Copyright Year: 2012
DOI: https://doi.org/10.1007/978-1-4614-0962-5_1