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2012 | OriginalPaper | Buchkapitel

1. Introduction

verfasst von : Qiaoyan Yu, Paul Ampadu

Erschienen in: Transient and Permanent Error Control for Networks-on-Chip

Verlag: Springer New York

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Abstract

Thanks to the rapid advancement of technology in semiconductor device fabrication, billions of transistors can be integrated to a single die [1–5]. Although the increasing chip density potentially facilitates systems-on-chip (SoCs) and chip multiprocessor (CMP) integrating hundreds or thousands of processing element/memory cores, several challenges prevent system further progress, such as design complexity, high-performance interconnect and scalable on-chip communication architecture [6–9]. Networks-on-chip (NoCs) becomes a promising paradigm, which manages the increasing interconnect complexity and facilitates the integration of various intellectual property (IP) cores [10–15].

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Nächstes Kapitel Existing Transient and Permanent Error Management in NoCs
Literatur
1.
Rusu S, Tam S, Muljono H, Stinson J, Ayers D, Chang J, Varada R, Ratta M, Kottapalli S (2009) A 45 nm 8-core enterprise Xeon® processor in. Proc IEEE Intl Solid-State Circuits Conf-Digest of Technical Papers 56–57
2.
Kurd NA et al (2010) Westmere: A family of 32 nm IA processors. in Proc IEEE Intl Solid-State Circuits Conf-Digest of Technical Papers 96–97
3.
Shin JL et al (2010) A 40 nm 16-core 128-thread CMT SPARC SoC processor. in Proc IEEE Intl Solid-State Circuits Conf-Digest of Technical Papers 98–99
4.
Wendel DF et al (2011) POWER7TM: A highly parallel, scalable multi-core high-end server processor. IEEE Journal of Solid-State Circuits 46:145–161CrossRef
5.
Anders MA et al (2010) A 41 Tb/s bisection-bandwidth 560 Gb/s/W streaming circuit-switched 8 × 8 mesh network-on-chip in 45 nm CMOS. in Proc IEEE Intl Solid-State Circuits Conf-Digest of Technical Papers 110–111
6.
Dally WJ, Towles B (2001) Route Packets, Not Wires: On-Chip Interconnection Networks. in Proc 38th Design Automation Conference (DAC’01) 684–689
7.
Sgroi M et al (2001) Addressing the system-on-a-chip interconnect woes through communication-based design. in Proc 38th Design Automation Conference (DAC’01) 667–672
8.
Benini L, De Micheli G (2002) Networks on Chips: A new SoC paradigm. Computer 35:70–78CrossRef
9.
Henkel J, Wolf W, Chakradhar S (2000) Network on chip: An architecture for billion transistor era. in Proc 18th IEEE NorChip Conf 166–173
10.
Benini L, De Micheli G (2001) Powering Networks on chips. in Proc Intl Symp System Synthesis 33–38
11.
Jantsch A, Tenhunen H (2003) Networks on Chip. Kluwer Academic Publishers
12.
Kim J, Park D, Nicopoulos C, Vijaykrishnan N, Das CR (2005) Design and analysis of an NoC architecture from performance, reliability and energy perspective. in Proc ACM/IEEE Symp on Architectures for Networking and Communications Syst (ANCS’05) 173–182
13.
Salminen E, Kulmala A, Hamalainen TD (2007) On network-on-chip comparison. in Proc 10th Euromicro Conf on Digital Syst Design Architectures, Methods and Tools (DSD 2007) 503–510
14.
Salminen E, Kulmala A, Hamalainen TD (2008) Survey of network-on-chip proposals. White paper, OCP-IP, 1–13
15.
Agarwal A, Iskander C, Shankar R (2009) Survey of Network on Chip (NoC) Architectures & Contributions. Engineering, Computing and Architecture 3:1–15
16.
Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) Cost considerations in Network on Chip. Integration - the VLSI journal, 38:19–42CrossRef
17.
Wiklund D, Liu D (2003) Socbus: switched network on chip for hard real time embedded systems. in Proc Intl Parallel and Distributed Processing Symp 1–8
18.
De Micheli G, Benini L (2007) Networks On Chips. Morgan Kaufmann, San Francisco
19.
Nilsson E, Millberg M, Oberg J, Jantsch A (2003) Load distribution with the proximity congestion awareness in a network on chip. in Proc DATE’03 1126–1127
20.
Liu J, Zheng L-R, Tenhunen H (2003) A guaranteed-throughput switch for network-on-chip. in Proc Intl Symp System-on-chip 31–34
21.
Millberg M, Nilsson E, Thid R, Jantsch A (2004) Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. in Proc DATE’04 8890–895
22.
Khorsandi S, Leon-Garcia A (1996) Robust non-probabilistic bounds for delay and throughput in credit-based flow control. in INFOCOMM 677–584
23.
Zeferino CA, Kreutz ME, Carro L, and Susin AA (2002) A study on communication issues for systems-on-chip. in Proc Symp Integr Circuits and Syst Design 121–126
24.
Radulescu A et al (2005) An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans on Computer-Aided Design of Integr Circuits and Syst (TCAD) 24:4–17CrossRef
25.
Zeferino C A, Santo FGME, Susin AA (2004) Paris: a parameterizable interconnect switch for networks-on-chip. in Proc Symp On Integr Circuits and Syst Design, 204–209
26.
Zeferino A, Susin AA (2003) SoCIN: a parametric and scalable network-on-chip. in Proc Symp On Integr Circuits and Syst Design 169–174
27.
Chan J, Parameswaran S (2004) Nocgen: a template based reuse methodology for networks on chip architecture. in Proc Intl Conf on VLSI Design 717–720
28.
Bertozzi D, Benini L (2004) Xpipes: a network on chip architecture for gigascale systems-on-chip. IEEE Circuits and Syst Magazine 4:18–31CrossRef
29.
Tamhankar RR, Murali S, De Micheli G (2005) Performance driven reliable link design for networks on chips. in Proc Asia and South Pacific Design Automation Conf (ASP-DAC’05) 749–754
30.
Pullini A, Angiolini F, Bertozzi D, Benini L (2005) Fault tolerance overhead in Network-on-chip flow control schemes. in Proc Symp On Integr Circuits and Syst Design (SBCI’05) 4–7
31.
32.
Ho R, Mai KW, Horowitz MA (2001) The future of wires. Proc IEEE, 89:490–504CrossRef
33.
Ho PS, Lee Ki-Don, Yoon S, Wang Guotao (2004) Reliability challenges and recent advance for Cu Interconnects. in Proc 5th Intl Conf on Thermal and Material Simulation and Experiments in Micro-electronics and Micro-Syst 15–16
34.
Mondal M, Wu X, Aziz A, Massoud Y (2006) Reliability analysis for on-chip networks under RC interconnect delay variation. in Proc Nanonet 1–5
35.
Ismail IY (2008) Interconnect design and limitations in nanoscale technologies. in Proc ISCAS'08 780–783
36.
Singhal R, Choi Gwan, Mahapatra R (2006) Information theoretic approach to address delay and reliability in long on-chip interconnects. in Proc ICCAD'06 310–314
37.
Abraham JA and Fuchs WK (1986) Fault and error models for VLSI. Proc IEEE 74:639–654CrossRef
38.
Constantinescu C (2003) Trends and challenges in VLSI circuit reliability. IEEE Micro 23:14–19CrossRef
39.
Karnik T, Hazucha P, Patel J (2004) Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans on Dependenable and Secure Computer 1:128–143CrossRef
40.
Maheshwari A, Koren I, Burleson W (2004) Accurate estimation of soft error rate (SER) in VLSI circuits. in Proc IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems (DFT'04) 377–385
41.
Chandra V, Aitken R (2008) Impact of technology and voltage scaling on the soft error susceptibility in nanoscale CMOS. in Proc DFT'08 114–122
42.
Calhoun BH et al (2008) Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proc IEEE 96:343–365CrossRef
43.
Owens JD et al (2007) Research challenges for on-chip interconnection networks. IEEE Micro 27:96–108CrossRef
44.
Vittal A, Chen LH, Marek-Sadowska M, Wang K-P, Yang S (1999) Crosstalk in VLSI interconnections. IEEE Trans on Computer-Aided Design of Integr Circuits and Syst (TCAD) 18:1817–1824CrossRef
45.
Aingaran K et al (2000) Coupling noise analysis for VLSI and ULSI circuits. in Proc IEEE International Symposiums on Quality Electronic Design (ISQED’00) 485–489
46.
Duan C, Calle VHC, Khatri SP (2009) Efficient on-chip crosstalk avoidance CODEC design. IEEE Trans Very Large Scale Integr (VLSI) Syst 17:551–560CrossRef
47.
Li L, Vijaykrishnan N, Kandemir M, Irwin MJ (2004) A crosstalk aware interconnect with variable cycle transmission. in Proc Design, Automation Test in Europe (DATE’04) 102–107
48.
Patel KN, Markov I L (2004) Error-correction and crosstalk avoidance in DSM busses. IEEE Trans Very Large Scale Integr (VLSI) Syst 12:1076–1080CrossRef
49.
Rossi D, Metra C, Nieuwland AK, Katoch A (2005) Exploiting ECC redundancy to minimize crosstalk impact. IEEE Design & Test of Computers 22:59–70CrossRef
50.
Pande PP, Ganguly A, Feero B, Belzer B, Grecu C (2006) Design of low power & reliable networks on chip through joint crosstalk avoidance and forward error correction coding. in Proc IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems (DFT’06) 466–476
51.
Ganguly A, Pande PP, Belzer B, Grecu C (2008) Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding. J Electron Test 24:67–81CrossRef
52.
Duan C, Tirumala A, Khatri SP (2001) Analysis and avoidance of crosstalk in on-chip buses. in Proc Hot Interconnects 133–138
53.
Fu B, Ampadu P (2010) Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction. IEEE Trans on Circuits and Systems–II: Express Briefs 57:399–403CrossRef
54.
Shanbhag N, Soumyanath K, Martin S (2000) Reliable low-power design in the presence of deep submicron noise. in Proc ISLPED'00 295–302
55.
Frantz AP, Cassel M, Kastensmidt FL, Cota E, Carro L (2007) Crosstalk- and SEU-aware networks on chips. IEEE Design & Test Computers, 24(4):340–350CrossRef
56.
Hoyos SE, Evans HDR, Daly E (2004) From satellite Ion flux data to SEU rate estimation. IEEE Trans Nuclear Science, 51:2927–2935CrossRef
57.
Zhang M, Shanbhag NR (2006) Soft-error-rate-analysis (SERA) methodology. IEEE Trans Computer-Aided Design of Integr Circuits and Syst (TCAD) 25:2140–2155CrossRef
58.
Bidokhti N (2010) SEU Concept to Reality (Allocation, Prediction, Mitigation). in Proc Reliability and Maintainability Symp (RAMS) 1–5
59.
Krishnamohan S, Mahapatra NR (2004) A highly-efficient technique for reducing soft errors in static CMOS circuits. in Proc ICCD'04 126–131
60.
61.
Lantz L II (1996) Soft errors induced by alpha particles. IEEE Trans Reliability 45:174–179CrossRef
62.
Heidel DF et al (2008) Alpha-particle-induced upsets in advanced CMOS circuits and technology. IBM J Research and Development 52:225–232CrossRef
63.
Ziegler JF (1996) Terrestrial cosmic rays. IBM J Research and Development 40:19–40CrossRef
64.
Gordon MS et al (2004) Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground. IEEE Trans on Nuclear Science 51:3427–3434CrossRef
65.
Wilkinson JD, Bounds C, Brown T, Gerbi B, Peltier J (2005) Cancer radiotherapy equipment as a cause of soft errors in electronic equipment. IEEE Trans Device and Materials Reliability 5:449–451CrossRef
66.
Franco L et al (2005) SEUs on commercial SRAM induced by low energy neutrons produced at a clinical linac facility. in Proc RADECS'05
67.
Khazaka R, Nakhla M (1998) Analysis of high-speed interconnects in the presence of electromagnetic interference. IEEE Trans Microwave Theory Tech 46:940–947CrossRef
68.
Hashimoto M, Yamaguchi J, Sato T, Onodera H (2005) Timing analysis considering temporal supply voltage fluctuation. in Proc ASP-DAC'05 1098–1101
69.
Balasubramanian A et al (2008) Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology. IEEE Trans Nuclear Science 55:2079–2084CrossRef
70.
Balasubramanian A, Sternberg AL, Bhuva BL, Massengill LW (2006) Crosstalk effects caused by single event hits in deep sub-micron CMOS technologies. IEEE Trans Nuclear Science 53:3306–3311CrossRef
71.
Agarwal K, Sylvester D, Blaauw D (2006) Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans Comput-Aided Des Integrated Circuits Syst 25:892–901CrossRef
72.
Sorensen HR, Daly EJ, Underwood CI, Ward J, Adams L (1990) The behavior of measured SEU at low altitude during periods of high solar activity [spacecraft memories]. IEEE Trans Nuclear Sciences 37:1938–1946CrossRef
73.
Li L, Vijaykrishnan N, Kandemir M, Irwin MJ (2003) Adaptive error protection for energy efficiency. in Proc ICCAD'03 2–7
74.
Aitken RC (1999) Nanometer technology effects on fault models for IC testing. IEEE Computer. 32(11):46–51CrossRef
75.
Abraham JA, Krishnamachary A, Tupuri RS (2002) A comprehensive fault model for deep submicron digital circuits. in Proc 1st IEEE Intl Work-shop on Electronic Design, Test and Applications (DELTA’02) 360–364
76.
Hawkins C, Keshavarzi A, Segura J (2003) A view from the bottom: nanometer technology AC parameter failures--why, where, and how to detect. in Proc 18th IEEE Intl Symp on Defect and fault Tolerance in VLSI Syst (DFT'03) 267–276
77.
Barsky R, Wagner IA (2004) Reliability and yield: a joint defect-oriented approach. in Proc 19th IEEE Intl Symp on Defect and fault Tolerance in VLSI Syst (DFT'04) 2–10
78.
Hussein MA, He J (2005) Materials' impact on interconnect process technology and reliability. IEEE Trans on Semiconductor Manufacturing 18:69–85CrossRef
79.
Lu Z, Huang W, Lach J, Stan M, Skadron K (2004) Interconnect lifetime prediction under dynamic stress for reliability-aware design. in Proc Intl Conf On Computer Aided Design (ICCAD’04) 327–334
80.
Alam MA, Mahapatra S (2005) A comprehensive model of PMOS NBTI degradation. Microelectronics Reliability, 45:71–81CrossRef
81.
Chess B, Larrabee T (1998) Logic testing of bridging faults in CMOS integrated circuits. IEEE Transactions on Computers 47:338–345CrossRef
82.
Rousset A et al (2007) Fast bridging fault diagnosis using logic information. in Proc 16th IEEE Asian Test Symp 33–38
83.
Hamdioui S, Al-Ars Z, van de Goor AJ (2006) Open and delay faults in CMOS RAM address decoders. IEEE Trans Computers 55:1630–1639CrossRef
84.
Fick D et al (2009) A highly resilient routing algorithm for fault tolerant NoCs. in Proc Design, Automation & Test in Europe Conf & Exhibition (DATE'09) 21–26
85.
Zhang Z, Greiner A, Taktak S (2008) A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip. in Proc IEEE Design Automation Conf (DAC’08) 441–446
Metadaten
Titel
Introduction
verfasst von
Qiaoyan Yu
Paul Ampadu
Copyright-Jahr
2012
Verlag
Springer New York
Buch
Transient and Permanent Error Control for Networks-on-Chip

Print ISBN: 978-1-4614-0961-8

Electronic ISBN: 978-1-4614-0962-5

Copyright-Jahr: 2012

DOI
https://doi.org/10.1007/978-1-4614-0962-5_1

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