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Published in:
2020 | OriginalPaper | Chapter
Investigation of Techniques to Recognize Optimal Power Structuring of Vedic Multiplier
Authors : P. Anitha, P. Ramanathan
Published in: Advances in Communication Systems and Networks
Publisher: Springer Singapore
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Abstract
Low power and high speed digital systems are essential for enhancing battery life of portable devices such as smartphones and digital computers. The integral part of any arithmetic and logic unit is adder. When compared to addition, subtraction and multiplication require more hardware resources and processing time. Low power consumption, delay and process variation parameters need to be taken care while designing the integrated circuit. In our proposed work, improved version of Vedic multiplier is designed and implemented by using CSA based on NEDFF. The proposed design offers low power dissipation and high speed. The power and delay results of existing and proposed multipliers are taken by using micro wind tool with technology of 90 nm. The experimental results signify that proposed Vedic multiplier using a CSA based on NEDFF provides 50% improvement in performance.