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Journal of Electronic Testing
Published in: Journal of Electronic Testing 3/2019

11-05-2019

Logic Locking: A Survey of Proposed Methods and Evaluation Metrics

Authors: Sophie Dupuis, Marie-Lise Flottes

Published in: Journal of Electronic Testing | Issue 3/2019

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Abstract

The outsourcing business model is dominating the semiconductor industry. Due to this loss of control over the design flow, several threats have become a major source of concern, including overproduction and IP overuse. For over a decade, several solutions have been proposed in the literature to counteract such threats. These solutions consist in hiding the behavior of the IPs/ICs until the design house securely unlocks them. This way, only unlocked IPs/ICs can be used properly while locked ones produce erroneous data. In this paper, we survey logic locking approaches and discuss locking quality in hiding expected behavior and in resisting to attacks.
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Metadata
Title
Logic Locking: A Survey of Proposed Methods and Evaluation Metrics
Authors
Sophie Dupuis
Marie-Lise Flottes
Publication date
11-05-2019
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 3/2019
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-019-05800-4

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