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Published in:
1997 | OriginalPaper | Chapter
Low Power Digital Multipliers
Author : Edwin de Angel
Published in: Application Specific Processors
Publisher: Springer US
Included in: Professional Book Archive
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CMOS digital multipliers have high power dissipation in comparison with other circuits due to carry propagation and spurious transitions. Techniques to reduce switching activity and improve the performance at the algorithm and circuit level are presented. A new concept to reduce switching activity using combinational self-timed elements and bypassing logic blocks to eliminate redundant operations is proposed.