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2012 | OriginalPaper | Chapter

4. Methods of Parameter Variations

Authors : Christoph Knoth, Ulf Schlichtmann, Bing Li, Min Zhang, Markus Olbrich, Emrah Acar, Uwe Eichler, Joachim Haase, André Lange, Michael Pronath

Published in: Process Variations and Probabilistic Integrated Circuit Design

Publisher: Springer New York

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Abstract

Chapter 4 presents various dedicated methods that support variability handling in the design process. Using these methods, the designer can analyze the effect of variations on his design and identify possible improvements.

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Footnotes
1
Finding corner cases is nontrivial not only because of the large number of parameters. For some parameters, such as temperature, nonlinear dependencies have been observed [4].
 
2
Note that electrical characteristics such as Isat or transconductance gm are simulation results, but not parameters of a transistor model like BSIM3.
 
Literature
1.
go back to reference Scheffer, L., Lavagno, L., Martin, G. (eds.): EDA for IC implementation, circuit design, and process technology. CRC Press (2006) Scheffer, L., Lavagno, L., Martin, G. (eds.): EDA for IC implementation, circuit design, and process technology. CRC Press (2006)
2.
go back to reference Kayssi, A.I., Sakallah, K.A., Mudge, T.N.: The impact of signal transition time on path delay computation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 40(5), 302–309 (1993)MATHCrossRef Kayssi, A.I., Sakallah, K.A., Mudge, T.N.: The impact of signal transition time on path delay computation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 40(5), 302–309 (1993)MATHCrossRef
3.
go back to reference Nardi, A., Neviani, A., Zanoni, E.: Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies. IEEE Transactions on Semiconductor Manufacturing (SM) 12(4), 396–402 (1999) Nardi, A., Neviani, A., Zanoni, E.: Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies. IEEE Transactions on Semiconductor Manufacturing (SM) 12(4), 396–402 (1999)
4.
go back to reference Dasdan, A., Hom, I.: Handling inverted temperature dependence in static timing analysis. ACM Transactions on Design Automation of Electronic Systems 11(2), 306–324 (2006)CrossRef Dasdan, A., Hom, I.: Handling inverted temperature dependence in static timing analysis. ACM Transactions on Design Automation of Electronic Systems 11(2), 306–324 (2006)CrossRef
5.
go back to reference Weber, M.: My head hurts, my timing stinks, and i don’t love on-chip variation. In: SNUG (2002) Weber, M.: My head hurts, my timing stinks, and i don’t love on-chip variation. In: SNUG (2002)
6.
go back to reference Incentia: Advanced on-chip-variation timing analysis. Tech. rep., Incentia Design Systems Inc. (2007) Incentia: Advanced on-chip-variation timing analysis. Tech. rep., Incentia Design Systems Inc. (2007)
7.
go back to reference Qian, J., Pullela, S., Pillage, L.: Modeling the “effective capacitance” for the RC interconnect of CMOS gates. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(12), 1526–1535 (1994)CrossRef Qian, J., Pullela, S., Pillage, L.: Modeling the “effective capacitance” for the RC interconnect of CMOS gates. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(12), 1526–1535 (1994)CrossRef
8.
go back to reference Celik, M., Pileggi, L., Odabasioglu, A.: IC Interconnect Analysis. Kluwer Academic Publishers (2004) Celik, M., Pileggi, L., Odabasioglu, A.: IC Interconnect Analysis. Kluwer Academic Publishers (2004)
11.
go back to reference Sakurai, T., Newton, A.R.: Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal of Solid-State Circuits SC 25(2), 584–594 (1990)CrossRef Sakurai, T., Newton, A.R.: Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal of Solid-State Circuits SC 25(2), 584–594 (1990)CrossRef
12.
go back to reference Hirata, A., Onodera, H., Tamaru, K.: Proposal of a timing model for CMOS logic gates driving a CRC pi load. In: ICCAD’98: Proceedings of the IEEE/ACM International Conference on Computer-aided Design, pp. 537–544. ACM, New York, NY, USA (1998) Hirata, A., Onodera, H., Tamaru, K.: Proposal of a timing model for CMOS logic gates driving a CRC pi load. In: ICCAD’98: Proceedings of the IEEE/ACM International Conference on Computer-aided Design, pp. 537–544. ACM, New York, NY, USA (1998)
13.
go back to reference Knoth, C., Kleeberger, V.B., Nordholz, P., Schlichtmann, U.: Fast and waveform independent characterization of current source models. In: IEEE/VIUF International Workshop on Behavioral Modeling and Simulation (BMAS), pp. 90–95 (2009) Knoth, C., Kleeberger, V.B., Nordholz, P., Schlichtmann, U.: Fast and waveform independent characterization of current source models. In: IEEE/VIUF International Workshop on Behavioral Modeling and Simulation (BMAS), pp. 90–95 (2009)
14.
go back to reference Croix, J., Wong, M.: Blade and razor: cell and interconnect delay analysis using current-based models. In: ACM/IEEE Design Automation Conference (DAC), pp. 386–389 (2003) Croix, J., Wong, M.: Blade and razor: cell and interconnect delay analysis using current-based models. In: ACM/IEEE Design Automation Conference (DAC), pp. 386–389 (2003)
15.
go back to reference Feldmann, P., Abbaspour, S., Sinha, D., Schaeffer, G., Banerji, R., Gupta, H.: Driver waveform computation for timing analysis with multiple voltage threshold driver models. In: ACM/IEEE Design Automation Conference (DAC), pp. 425–428 (2008) Feldmann, P., Abbaspour, S., Sinha, D., Schaeffer, G., Banerji, R., Gupta, H.: Driver waveform computation for timing analysis with multiple voltage threshold driver models. In: ACM/IEEE Design Automation Conference (DAC), pp. 425–428 (2008)
16.
go back to reference Liu, B., Kahng, A.B.: Statistical gate level simulation via voltage controlled current source models. In: IEEE International Behavioral Modeling and Simulation Workshop (2006) Liu, B., Kahng, A.B.: Statistical gate level simulation via voltage controlled current source models. In: IEEE International Behavioral Modeling and Simulation Workshop (2006)
17.
go back to reference Wang, X., Kasnavi, A., Levy, H.: An efficient method for fast delay and SI calculation using current source models. In: IEEE International Symposium on Quality Electronic Design, pp. 57–61. IEEE Computer Society, Washington, DC, USA (2008) Wang, X., Kasnavi, A., Levy, H.: An efficient method for fast delay and SI calculation using current source models. In: IEEE International Symposium on Quality Electronic Design, pp. 57–61. IEEE Computer Society, Washington, DC, USA (2008)
18.
go back to reference Kashyap, C., Amin, C., Menezes, N., Chiprout, E.: A nonlinear cell macromodel for digital applications. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 678–685 (2007) Kashyap, C., Amin, C., Menezes, N., Chiprout, E.: A nonlinear cell macromodel for digital applications. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 678–685 (2007)
19.
go back to reference Li, P., Feng, Z., Acar, E.: Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis. IEEE Transactions on VLSI Systems 15(11), 1205–1214 (2007)CrossRef Li, P., Feng, Z., Acar, E.: Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis. IEEE Transactions on VLSI Systems 15(11), 1205–1214 (2007)CrossRef
20.
go back to reference Goel, A., Vrudhula, S.: Current source based standard cell model for accurate signal integrity and timing analysis. In: Design, Automation and Test in Europe (DATE), pp. 574–579 (2008) Goel, A., Vrudhula, S.: Current source based standard cell model for accurate signal integrity and timing analysis. In: Design, Automation and Test in Europe (DATE), pp. 574–579 (2008)
22.
go back to reference Fatemi, H., Nazarian, S., Pedram, M.: Statistical logic cell delay analysis using a current-based model. In: ACM/IEEE Design Automation Conference (DAC), pp. 253–256 (2006) Fatemi, H., Nazarian, S., Pedram, M.: Statistical logic cell delay analysis using a current-based model. In: ACM/IEEE Design Automation Conference (DAC), pp. 253–256 (2006)
22.
go back to reference Fatemi, H., Nazarian, S., Pedram, M.: Statistical logic cell delay analysis using a current-based model. In: ACM/IEEE Design Automation Conference (DAC), pp. 253–256 (2006) Fatemi, H., Nazarian, S., Pedram, M.: Statistical logic cell delay analysis using a current-based model. In: ACM/IEEE Design Automation Conference (DAC), pp. 253–256 (2006)
23.
go back to reference Mitev, A., Ganesan, D., Shanmugasundaram, D., Cao, Y., Wang, J.M.: A robust finite-point based gate model considering process variations. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 692–697 (2007) Mitev, A., Ganesan, D., Shanmugasundaram, D., Cao, Y., Wang, J.M.: A robust finite-point based gate model considering process variations. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 692–697 (2007)
24.
go back to reference Amin, C., Kashyap, C., Menezes, N., Killpack, K., Chiprout, E.: A multi-port current source model for multiple-input switching effects in CMOS library cells. In: ACM/IEEE Design Automation Conference (DAC), pp. 247–252 (2006) Amin, C., Kashyap, C., Menezes, N., Killpack, K., Chiprout, E.: A multi-port current source model for multiple-input switching effects in CMOS library cells. In: ACM/IEEE Design Automation Conference (DAC), pp. 247–252 (2006)
25.
go back to reference Dabas, S., Dong, N., Roychowdhury, J.: Automated extraction of accurate delay/timing macromodels of digital gates and latches using trajectory piecewise methods. In: Asia and South Pacific Design Automation Conference, pp. 361–366 (2007) Dabas, S., Dong, N., Roychowdhury, J.: Automated extraction of accurate delay/timing macromodels of digital gates and latches using trajectory piecewise methods. In: Asia and South Pacific Design Automation Conference, pp. 361–366 (2007)
26.
go back to reference Knoth, C., Kleeberger, V.B., Schmidt, M., Li, B., Schlichtmann, U.: Transfer system models of logic gates for waveform-based timing analysis. In: International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), pp. 247–252 (2008) Knoth, C., Kleeberger, V.B., Schmidt, M., Li, B., Schlichtmann, U.: Transfer system models of logic gates for waveform-based timing analysis. In: International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), pp. 247–252 (2008)
27.
go back to reference Goel, A., Vrudhula, S.: Statistical waveform and current source based standard cell models for accurate timing analysis. In: ACM/IEEE Design Automation Conference (DAC), pp. 227–230 (2008) Goel, A., Vrudhula, S.: Statistical waveform and current source based standard cell models for accurate timing analysis. In: ACM/IEEE Design Automation Conference (DAC), pp. 227–230 (2008)
28.
go back to reference Zolotov, V., Xiong, J., Abbaspour, S., Hathaway, D.J., Visweswariah, C.: Compact modeling of variational waveforms. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 705–712. IEEE Press, Piscataway, NJ, USA (2007) Zolotov, V., Xiong, J., Abbaspour, S., Hathaway, D.J., Visweswariah, C.: Compact modeling of variational waveforms. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 705–712. IEEE Press, Piscataway, NJ, USA (2007)
29.
go back to reference Yeo, K.S., Roy, K.: Low Voltage, Low Power VLSI Subsystems. McGraw-Hill Professional (2004) Yeo, K.S., Roy, K.: Low Voltage, Low Power VLSI Subsystems. McGraw-Hill Professional (2004)
30.
go back to reference Narendra, S., Blaauw, D., Devgan, A., Najm, F.: Leakage issues in IC design: Trends, estimation and avoidance. In: Proc. ICCAD 2003, Tutorial (2003) Narendra, S., Blaauw, D., Devgan, A., Najm, F.: Leakage issues in IC design: Trends, estimation and avoidance. In: Proc. ICCAD 2003, Tutorial (2003)
79.
go back to reference Rao, R.R., Devgan, A., Blaauw, D., Sylvester, D.: Parametric yield estimation considering leakage variability. In: Proc. DAC 2004, pp. 442–447 (2004) Rao, R.R., Devgan, A., Blaauw, D., Sylvester, D.: Parametric yield estimation considering leakage variability. In: Proc. DAC 2004, pp. 442–447 (2004)
32.
go back to reference Agarwal, A., Kang, K., Roy, K.: Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. In: ICCAD, pp. 736–741 (2005) Agarwal, A., Kang, K., Roy, K.: Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. In: ICCAD, pp. 736–741 (2005)
33.
go back to reference Li, T., Zhang, W., Yu, Z.: Full-chip leakage analysis in nano-scale technologies: Mechanisms, variation sources, and verification. In: Proc. DAC 2008, pp. 594–599 (2008) Li, T., Zhang, W., Yu, Z.: Full-chip leakage analysis in nano-scale technologies: Mechanisms, variation sources, and verification. In: Proc. DAC 2008, pp. 594–599 (2008)
34.
go back to reference Li, X., Le, J., Pileggi, L.T., Strojwas, A.: Projection-based performance modeling for inter/intra-die variations. In: Proc. ICCAD 2005, pp. 721–727 (2005) Li, X., Le, J., Pileggi, L.T., Strojwas, A.: Projection-based performance modeling for inter/intra-die variations. In: Proc. ICCAD 2005, pp. 721–727 (2005)
35.
go back to reference Li, X., Le, J., Pileggi, L.T.: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. In: Proc. DAC 2006, pp. 103–108 (2006) Li, X., Le, J., Pileggi, L.T.: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. In: Proc. DAC 2006, pp. 103–108 (2006)
36.
go back to reference Zhuo, F., Li, P.: Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression. In: Proc. ICCAD 2006, pp. 868–875 (2006) Zhuo, F., Li, P.: Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression. In: Proc. ICCAD 2006, pp. 868–875 (2006)
37.
go back to reference Mitev, A., Marefat, M., Ma, D., Wang, J.M.: Principle hessian direction based parameter reduction with process variation. In: Proc. ICCAD 2007, pp. 632–637 (2007) Mitev, A., Marefat, M., Ma, D., Wang, J.M.: Principle hessian direction based parameter reduction with process variation. In: Proc. ICCAD 2007, pp. 632–637 (2007)
38.
go back to reference Hastie, T., Tibshirani, R., Friedman, J.: The Elements of Statistical Learning. Springer (2001) Hastie, T., Tibshirani, R., Friedman, J.: The Elements of Statistical Learning. Springer (2001)
39.
go back to reference Bellman, R.E.: Adaptive Control Processes. Princeton University Press (1961) Bellman, R.E.: Adaptive Control Processes. Princeton University Press (1961)
43.
go back to reference Geman, S., Bienenstock, E., Doursat, R.: Neural networks and the bias/variance dilemma. Neural Computation 4(1), 1–58 (1992)CrossRef Geman, S., Bienenstock, E., Doursat, R.: Neural networks and the bias/variance dilemma. Neural Computation 4(1), 1–58 (1992)CrossRef
41.
go back to reference Sugiyama, M., Rubens, N.: Active learning with model selection in linear regression. In: The SIAM International Conference on Data Mining, pp. 518–529 (2008) Sugiyama, M., Rubens, N.: Active learning with model selection in linear regression. In: The SIAM International Conference on Data Mining, pp. 518–529 (2008)
42.
go back to reference Maimon, O., Rokach, L.: Data Mining and Knowledge Discovery Handbook. Springer (2005) Maimon, O., Rokach, L.: Data Mining and Knowledge Discovery Handbook. Springer (2005)
43.
go back to reference Geman, S., Bienenstock, E., Doursat, R.: Neural networks and the bias/variance dilemma. Neural Computation 4(1), 1–58 (1992)CrossRef Geman, S., Bienenstock, E., Doursat, R.: Neural networks and the bias/variance dilemma. Neural Computation 4(1), 1–58 (1992)CrossRef
44.
go back to reference Berk, R.A.: Statistical Learning from a Regression Perspective. Springer (2008) Berk, R.A.: Statistical Learning from a Regression Perspective. Springer (2008)
45.
go back to reference Cadence: Clock Domain Crossing (White Paper) (2004) Cadence: Clock Domain Crossing (White Paper) (2004)
46.
go back to reference Shenoy, N., Brayton, R., Sangiovanni-Vincentelli, A.: Minimum padding to satisfy short path constraints. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 156–161 (1993) Shenoy, N., Brayton, R., Sangiovanni-Vincentelli, A.: Minimum padding to satisfy short path constraints. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 156–161 (1993)
47.
go back to reference Zhang, L., Tsai, J., Chen, W., Hu, Y., Chen, C.C.P.: Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 941–946 (2006) Zhang, L., Tsai, J., Chen, W., Hu, Y., Chen, C.C.P.: Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 941–946 (2006)
48.
go back to reference Kamikawai, R., Yamada, M., Chiba, T., Furumaya, K., Tsuchiya, Y.: A critical path delay check system. In: ACM/IEEE Design Automation Conference (DAC), pp. 118–123 (1981) Kamikawai, R., Yamada, M., Chiba, T., Furumaya, K., Tsuchiya, Y.: A critical path delay check system. In: ACM/IEEE Design Automation Conference (DAC), pp. 118–123 (1981)
49.
go back to reference Pilling, D.J., Sun, H.B.: Computer-aided prediction of delays in LSI logic systems. In: ACM/IEEE Design Automation Conference (DAC), pp. 182–186 (1973) Pilling, D.J., Sun, H.B.: Computer-aided prediction of delays in LSI logic systems. In: ACM/IEEE Design Automation Conference (DAC), pp. 182–186 (1973)
50.
go back to reference Sasaki, T., Yamada, A., Aoyama, T., Hasegawa, K., Kato, S., Sato, S.: Hierarchical design verification for large digital systems. In: ACM/IEEE Design Automation Conference (DAC), pp. 105–112 (1981) Sasaki, T., Yamada, A., Aoyama, T., Hasegawa, K., Kato, S., Sato, S.: Hierarchical design verification for large digital systems. In: ACM/IEEE Design Automation Conference (DAC), pp. 105–112 (1981)
51.
go back to reference Hitchcock, R.B.: Timing verification and the timing analysis program. In: ACM/IEEE Design Automation Conference (DAC), pp. 594–604 (1982) Hitchcock, R.B.: Timing verification and the timing analysis program. In: ACM/IEEE Design Automation Conference (DAC), pp. 594–604 (1982)
52.
go back to reference Hitchcock, R.B., Smith, G.L., Cheng, D.D.: Timing analysis of computer hardware. IBM Journal Research Development 26(1), 100–105 (1982)CrossRef Hitchcock, R.B., Smith, G.L., Cheng, D.D.: Timing analysis of computer hardware. IBM Journal Research Development 26(1), 100–105 (1982)CrossRef
53.
go back to reference Maheshwari, N., Sapatnekar, S.S.: Timing Analysis and Optimization of Sequential Circuits. Kluwer Academic Publishers (1999) Maheshwari, N., Sapatnekar, S.S.: Timing Analysis and Optimization of Sequential Circuits. Kluwer Academic Publishers (1999)
56.
go back to reference Feldman, D., Fox, M.: Probability, The Mathematics of Uncertainty. Marcel Dekker, Inc (1991)MATH Feldman, D., Fox, M.: Probability, The Mathematics of Uncertainty. Marcel Dekker, Inc (1991)MATH
55.
go back to reference Visweswariah, C., Ravindran, K., Kalafala, K., Walker, S., Narayan, S.: First-order incremental block-based statistical timing analysis. In: ACM/IEEE Design Automation Conference (DAC), pp. 331–336 (2004) Visweswariah, C., Ravindran, K., Kalafala, K., Walker, S., Narayan, S.: First-order incremental block-based statistical timing analysis. In: ACM/IEEE Design Automation Conference (DAC), pp. 331–336 (2004)
56.
go back to reference Feldman, D., Fox, M.: Probability, The Mathematics of Uncertainty. Marcel Dekker, Inc (1991)MATH Feldman, D., Fox, M.: Probability, The Mathematics of Uncertainty. Marcel Dekker, Inc (1991)MATH
58.
go back to reference Chang, H., Sapatnekar, S.S.: Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 621–625 (2003) Chang, H., Sapatnekar, S.S.: Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 621–625 (2003)
59.
go back to reference Agarwal, A., Zolotov, V., Blaauw, D.T.: Statistical timing analysis using bounds and selective enumeration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(9), 1243–1260 (2003)CrossRef Agarwal, A., Zolotov, V., Blaauw, D.T.: Statistical timing analysis using bounds and selective enumeration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(9), 1243–1260 (2003)CrossRef
60.
go back to reference Devgan, A., Kashyap, C.: Block-based static timing analysis with uncertainty. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 607–614 (2003) Devgan, A., Kashyap, C.: Block-based static timing analysis with uncertainty. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 607–614 (2003)
61.
go back to reference Zhang, L., Hu, Y., Chen, C.P.: Block based statistical timing analysis with extended canonical timing model. In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 250–253 (2005) Zhang, L., Hu, Y., Chen, C.P.: Block based statistical timing analysis with extended canonical timing model. In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 250–253 (2005)
62.
go back to reference Zhan, Y., Strojwas, A.J., Li, X., Pileggi, L.T., Newmark, D., Sharma, M.: Correlation-aware statistical timing analysis with non-Gaussian delay distributions. In: ACM/IEEE Design Automation Conference (DAC), pp. 77–82 (2005) Zhan, Y., Strojwas, A.J., Li, X., Pileggi, L.T., Newmark, D., Sharma, M.: Correlation-aware statistical timing analysis with non-Gaussian delay distributions. In: ACM/IEEE Design Automation Conference (DAC), pp. 77–82 (2005)
63.
go back to reference Feng, Z., Li, P., Zhan, Y.: Fast second-order statistical static timing analysis using parameter dimension reduction. In: ACM/IEEE Design Automation Conference (DAC), pp. 244–249 (2007) Feng, Z., Li, P., Zhan, Y.: Fast second-order statistical static timing analysis using parameter dimension reduction. In: ACM/IEEE Design Automation Conference (DAC), pp. 244–249 (2007)
64.
go back to reference Zhang, L., Chen, W., Hu, Y., Gubner, J.A., Chen, C.C.P.: Correlation-preserved non-Gaussian statistical timing analysis with quadratic timing model. In: ACM/IEEE Design Automation Conference (DAC), pp. 83–88 (2005) Zhang, L., Chen, W., Hu, Y., Gubner, J.A., Chen, C.C.P.: Correlation-preserved non-Gaussian statistical timing analysis with quadratic timing model. In: ACM/IEEE Design Automation Conference (DAC), pp. 83–88 (2005)
66.
go back to reference Singh, J., Sapatnekar, S.: Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis. In: ACM/IEEE Design Automation Conference (DAC), pp. 155–160 (2006) Singh, J., Sapatnekar, S.: Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis. In: ACM/IEEE Design Automation Conference (DAC), pp. 155–160 (2006)
67.
go back to reference Singh, J., Sapatnekar, S.S.: A scalable statistical static timing analyzer incorporating correlated non-Gaussian and Gaussian parameter variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(1), 160–173 (2008)CrossRef Singh, J., Sapatnekar, S.S.: A scalable statistical static timing analyzer incorporating correlated non-Gaussian and Gaussian parameter variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(1), 160–173 (2008)CrossRef
68.
go back to reference Li, X., Le, J., Gopalakrishnan, P., Pileggi, L.T.: Asymptotic probability extraction for non-normal distributions of circuit performance. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2004) Li, X., Le, J., Gopalakrishnan, P., Pileggi, L.T.: Asymptotic probability extraction for non-normal distributions of circuit performance. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2004)
69.
go back to reference Chang, H., Zolotov, V., Narayan, S., Visweswariah, C.: Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions. In: ACM/IEEE Design Automation Conference (DAC), pp. 71–76 (2005) Chang, H., Zolotov, V., Narayan, S., Visweswariah, C.: Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions. In: ACM/IEEE Design Automation Conference (DAC), pp. 71–76 (2005)
70.
go back to reference Agarwal, A., Blaauw, D., Zolotov, V., Vrudhula, S.: Statistical timing analysis using bounds. In: Design, Automation and Test in Europe (DATE), pp. 62–67 (2003) Agarwal, A., Blaauw, D., Zolotov, V., Vrudhula, S.: Statistical timing analysis using bounds. In: Design, Automation and Test in Europe (DATE), pp. 62–67 (2003)
71.
go back to reference Agarwal, A., Blaauw, D., Zolotov, V., Vrudhula, S.: Computation and refinement of statistical bounds on circuit delay. In: ACM/IEEE Design Automation Conference (DAC), pp. 348–353 (2003) Agarwal, A., Blaauw, D., Zolotov, V., Vrudhula, S.: Computation and refinement of statistical bounds on circuit delay. In: ACM/IEEE Design Automation Conference (DAC), pp. 348–353 (2003)
72.
go back to reference Agarwal, A., Blaauw, D., Zolotov, V., Sundareswaran, S., Zhao, M., Gala, K., Panda, R.: Path-based statistical timing analysis considering inter- and intra-die correlations. In: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 16–21 (2002) Agarwal, A., Blaauw, D., Zolotov, V., Sundareswaran, S., Zhao, M., Gala, K., Panda, R.: Path-based statistical timing analysis considering inter- and intra-die correlations. In: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 16–21 (2002)
73.
go back to reference Orshansky, M., Bandyopadhyay, A.: Fast statistical timing analysis handling arbitrary delay correlations. In: ACM/IEEE Design Automation Conference (DAC), pp. 337–342 (2004) Orshansky, M., Bandyopadhyay, A.: Fast statistical timing analysis handling arbitrary delay correlations. In: ACM/IEEE Design Automation Conference (DAC), pp. 337–342 (2004)
74.
go back to reference Li, X., Le, J., Celik, M., Pileggi, L.T.: Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(6), 1041–1054 (2008)CrossRef Li, X., Le, J., Celik, M., Pileggi, L.T.: Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(6), 1041–1054 (2008)CrossRef
75.
go back to reference Mukhopadhyay, S., Raychowdhury, A., Roy, K.: Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. In: DAC ’03: Proceedings of the 40th annual Design Automation Conference, pp. 169–174. ACM, New York, NY, USA (2003). DOI 10.1145/775832.775877 Mukhopadhyay, S., Raychowdhury, A., Roy, K.: Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. In: DAC ’03: Proceedings of the 40th annual Design Automation Conference, pp. 169–174. ACM, New York, NY, USA (2003). DOI 10.1145/775832.775877
76.
go back to reference Kao, J., Narendra, S., Chandrakasan, A.: Subthreshold leakage modeling and reduction techniques. In: Proc. ICCAD, 2002, pp. 141–148 (2002)CrossRef Kao, J., Narendra, S., Chandrakasan, A.: Subthreshold leakage modeling and reduction techniques. In: Proc. ICCAD, 2002, pp. 141–148 (2002)CrossRef
77.
go back to reference Acar, E., Devgan, A., Nassif, S.R.: Leakage and leakage sensitivity computation for combinational circuits. Journal of Low Power Europe 1(2), 1–10 (2005) Acar, E., Devgan, A., Nassif, S.R.: Leakage and leakage sensitivity computation for combinational circuits. Journal of Low Power Europe 1(2), 1–10 (2005)
78.
go back to reference Jiang, W., Tiwari, V., de la Iglesia, E., Sinha, A.: Topological analysis for leakage prediction of digital circuits. In: Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings., pp. 39–44 (2002) Jiang, W., Tiwari, V., de la Iglesia, E., Sinha, A.: Topological analysis for leakage prediction of digital circuits. In: Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings., pp. 39–44 (2002)
79.
go back to reference Rao, R.R., Devgan, A., Blaauw, D., Sylvester, D.: Parametric yield estimation considering leakage variability. In: Proc. DAC 2004, pp. 442–447 (2004) Rao, R.R., Devgan, A., Blaauw, D., Sylvester, D.: Parametric yield estimation considering leakage variability. In: Proc. DAC 2004, pp. 442–447 (2004)
80.
go back to reference Favalli, M., Benini, L.: Analysis of glitch power dissipation in CMOS ICs. In: ISLPED ’95: Proceedings of the 1995 international symposium on Low power design, pp. 123–128. ACM, New York, NY, USA (1995). DOI 10.1145/224081.224103 Favalli, M., Benini, L.: Analysis of glitch power dissipation in CMOS ICs. In: ISLPED ’95: Proceedings of the 1995 international symposium on Low power design, pp. 123–128. ACM, New York, NY, USA (1995). DOI 10.1145/224081.224103
81.
go back to reference Najm, F., Burch, R., Yang, P., Hajj, I.: CREST - a current estimator for CMOS circuits. In: IEEE International Conference on Computer-Aided Design, pp. 204–207 (1988) Najm, F., Burch, R., Yang, P., Hajj, I.: CREST - a current estimator for CMOS circuits. In: IEEE International Conference on Computer-Aided Design, pp. 204–207 (1988)
82.
go back to reference Wang, L., Olbrich, M., Barke, E., Büchner, T., Bühler, M.: Fast dynamic power estimation considering glitch filtering. In: SOCC, pp. 361–364 (2009) Wang, L., Olbrich, M., Barke, E., Büchner, T., Bühler, M.: Fast dynamic power estimation considering glitch filtering. In: SOCC, pp. 361–364 (2009)
83.
go back to reference Häußler, R., Kinzelbach, H.: Sensitivity-based stochastic analysis method for power variations. In: ITG Fachbericht 196, 9. ITG/GMM-Fachtagung, ANALOG’06, Entwicklung von Analogschaltungen mit CAE-Methoden, pp. 125–130. Dresden (2006) Häußler, R., Kinzelbach, H.: Sensitivity-based stochastic analysis method for power variations. In: ITG Fachbericht 196, 9. ITG/GMM-Fachtagung, ANALOG’06, Entwicklung von Analogschaltungen mit CAE-Methoden, pp. 125–130. Dresden (2006)
84.
go back to reference SAE International, Electronic Design Automation Standards Committee: J2748 VHDL-AMS Statistical Packages (2006) SAE International, Electronic Design Automation Standards Committee: J2748 VHDL-AMS Statistical Packages (2006)
85.
go back to reference Christen, E., Bedrosian, D., Haase, J.: Statistical modeling with VHDL-AMS. In: Forum on Specification and Design Languages, FDL’07, pp. 44–49. ECSI, Barcelona (2007) Christen, E., Bedrosian, D., Haase, J.: Statistical modeling with VHDL-AMS. In: Forum on Specification and Design Languages, FDL’07, pp. 44–49. ECSI, Barcelona (2007)
86.
go back to reference Synopsys, Inc.: PrimeTime User Guide, B-2008.12 edn. (2008) Synopsys, Inc.: PrimeTime User Guide, B-2008.12 edn. (2008)
88.
go back to reference Schenkel, F., Pronath, M., Zizala, S., Schwencker, R., Graeb, H., Antreich, K.: Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search. In: DAC, pp. 858–863 (2001) Schenkel, F., Pronath, M., Zizala, S., Schwencker, R., Graeb, H., Antreich, K.: Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search. In: DAC, pp. 858–863 (2001)
89.
go back to reference Graeb, H., Zizala, S., Eckmueller, J., Antreich, K.: The sizing rules method for analog integrated circuit design. In: ICCAD, pp. 343–349 (2001) Graeb, H., Zizala, S., Eckmueller, J., Antreich, K.: The sizing rules method for analog integrated circuit design. In: ICCAD, pp. 343–349 (2001)
90.
go back to reference Stehr, G., Pronath, M., Schenkel, F., Graeb, H., Antreich, K.: Initial sizing of analog integrated circuits by centering within topology-given implicit specifications. In: ICCAD (2003) Stehr, G., Pronath, M., Schenkel, F., Graeb, H., Antreich, K.: Initial sizing of analog integrated circuits by centering within topology-given implicit specifications. In: ICCAD (2003)
91.
go back to reference Rooch, K.H., Sobe, U., Pronath, M.: Circuit design-for-yield (DFY) for a 110dB Op-Amp for automotive and sensor applications. In: ITG Fachbericht 196, 9. ITG/GMM-Fachtagung, ANALOG’06, Entwicklung von Analogschaltungen mit CAE-Methoden, pp. 119–123. Dresden (2006) Rooch, K.H., Sobe, U., Pronath, M.: Circuit design-for-yield (DFY) for a 110dB Op-Amp for automotive and sensor applications. In: ITG Fachbericht 196, 9. ITG/GMM-Fachtagung, ANALOG’06, Entwicklung von Analogschaltungen mit CAE-Methoden, pp. 119–123. Dresden (2006)
92.
go back to reference Schwencker, R., Schenkel, F., Graeb, H., Antreich, K.: The generalized boundary curve – A common method for automatic nominal design and design centering of analog circuits. In: DATE, pp. 42–47 (2000) Schwencker, R., Schenkel, F., Graeb, H., Antreich, K.: The generalized boundary curve – A common method for automatic nominal design and design centering of analog circuits. In: DATE, pp. 42–47 (2000)
93.
go back to reference Antreich, K.J., Graeb, H.E.: Circuit optimization driven by worst-case distances. In: The Best of ICCAD – 20 Years of Excellence in Computer-Aided Design, pp. 585–595. Kluwer Academic Publishers (2003) Antreich, K.J., Graeb, H.E.: Circuit optimization driven by worst-case distances. In: The Best of ICCAD – 20 Years of Excellence in Computer-Aided Design, pp. 585–595. Kluwer Academic Publishers (2003)
94.
go back to reference Montgomery, D.: Design and Analysis of Experiments, 3rd edn. John Wiley & Sons, New York (1991)MATH Montgomery, D.: Design and Analysis of Experiments, 3rd edn. John Wiley & Sons, New York (1991)MATH
95.
go back to reference Sohrmann, C., Muche, L., Haase, J.: Accurate approximation to the probability of critical performance. In: 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, pp. 93–97 (2008) Sohrmann, C., Muche, L., Haase, J.: Accurate approximation to the probability of critical performance. In: 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, pp. 93–97 (2008)
96.
go back to reference Pehl, M., Graeb, H.: RaGAzi: A random and gradient-based approach to analog sizing for mixed discrete and continuous parameters. In: Integrated Circuits, ISIC ’09. Proceedings of the 2009 12th International Symposium on, pp. 113–116 (2009) Pehl, M., Graeb, H.: RaGAzi: A random and gradient-based approach to analog sizing for mixed discrete and continuous parameters. In: Integrated Circuits, ISIC ’09. Proceedings of the 2009 12th International Symposium on, pp. 113–116 (2009)
97.
go back to reference Hartung, J.: Statistik: Hand- und Lehrbuch der angewandten Statistik, 12 edn. R. Oldenbourg (1999) Hartung, J.: Statistik: Hand- und Lehrbuch der angewandten Statistik, 12 edn. R. Oldenbourg (1999)
98.
go back to reference Kotz, S., Johnson, N.: Process capability indices. Chapman & Hall, London (1993) Kotz, S., Johnson, N.: Process capability indices. Chapman & Hall, London (1993)
99.
go back to reference Rinne, H., Mittag, H.J.: Prozessfähigkeitsmessung für die industrielle Praxis. Hanser (1999) Rinne, H., Mittag, H.J.: Prozessfähigkeitsmessung für die industrielle Praxis. Hanser (1999)
100.
go back to reference Aftab, S., Styblinski, M.: IC variability minimization using a new C p and C pk based variability/performance measure. In: ISCAS ’94., 1994 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 149–152 (1994) Aftab, S., Styblinski, M.: IC variability minimization using a new C p and C pk based variability/performance measure. In: ISCAS ’94., 1994 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 149–152 (1994)
101.
go back to reference ISO 21747: Statistical methods – Process performance and capability statistics for measured quality characteristics (2006) ISO 21747: Statistical methods – Process performance and capability statistics for measured quality characteristics (2006)
102.
go back to reference Bennett, B.: On multivariate coefficients of variation. Statistical Papers 18(2), 123–128 (1977). Springer, Berlin Bennett, B.: On multivariate coefficients of variation. Statistical Papers 18(2), 123–128 (1977). Springer, Berlin
103.
go back to reference Lange, A., Muche, L., Haase, J., Mau, H.: Robustness characterization of standard cell libraries. In: DASS 2010 – Dresdner Arbeitstagung Schaltungs- und Systementwurf, pp. 13–18 (2010) Lange, A., Muche, L., Haase, J., Mau, H.: Robustness characterization of standard cell libraries. In: DASS 2010 – Dresdner Arbeitstagung Schaltungs- und Systementwurf, pp. 13–18 (2010)
104.
go back to reference Marques de Sá, J.: Applied Statistics Using SPSS, STATISTICA, MATLAB and R, 2nd edn. Springer (2007) Marques de Sá, J.: Applied Statistics Using SPSS, STATISTICA, MATLAB and R, 2nd edn. Springer (2007)
105.
go back to reference International Technology Roadmap for Semiconductors: System drivers (2007) International Technology Roadmap for Semiconductors: System drivers (2007)
106.
go back to reference Borel, J. (ed.): European Design Automation Roadmap. Parais (2009) Borel, J. (ed.): European Design Automation Roadmap. Parais (2009)
Metadata
Title
Methods of Parameter Variations
Authors
Christoph Knoth
Ulf Schlichtmann
Bing Li
Min Zhang
Markus Olbrich
Emrah Acar
Uwe Eichler
Joachim Haase
André Lange
Michael Pronath
Copyright Year
2012
Publisher
Springer New York
DOI
https://doi.org/10.1007/978-1-4419-6621-6_4