Minimizing Total Weighted Tardiness on Parallel Batch Process Machines Using Genetic Algorithms

Recently, the electronics industry has become the largest industry in the world. A key aspect of this industry is the manufacturing of integrated circuits. In the past, sources of reducing costs were decreasing the size of the chips, increasing the wafer sizes and improving the yield, simultaneously with efforts to improve operational processes inside the wafer fabrication facilities (wafer fab). Currently, it seems that the improvement of operational processes creates the best opportunity to realize the necessary cost reductions [6].