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Journal of Electronic Testing
Published in: Journal of Electronic Testing 6/2013

01-12-2013

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

Authors: Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai

Published in: Journal of Electronic Testing | Issue 6/2013

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Abstract

This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.
previous article Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling
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Appendix
Available only for authorised users
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Metadata
Title
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity
Authors
Satoshi Uemori
Masamichi Ishii
Haruo Kobayashi
Daiki Hirabayashi
Yuta Arakawa
Yuta Doi
Osamu Kobayashi
Tatsuji Matsuura
Kiichi Niitsu
Yuji Yano
Tatsuhiro Gake
Takahiro J. Yamaguchi
Nobukazu Takai
Publication date
01-12-2013
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 6/2013
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-013-5408-6

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