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General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing Factors Read chapter Read first chapter

2018 | OriginalPaper | Chapter

5. Optimization of Digital Circuits with Consideration of DF

Author : Vazgen Melikyan

Published in: Simulation and Optimization of Digital Circuits

Publisher: Springer International Publishing

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Abstract

An algorithm for optimizing the critical timing paths of digital circuits, taking into account the influence of destabilizing factors with the minimal growth of power consumption by the circuit is described. The algorithm is tested on digital circuits of the ISCAS89 series. An algorithm to solve the problem of reducing the level of power consumption of digital circuits, taking into account the influence of destabilizing factors at the expense of the use of the speed margin in the design options of digital circuits is also described.

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previous chapter Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DF
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Metadata
Title
Optimization of Digital Circuits with Consideration of DF
Author
Vazgen Melikyan
Copyright Year
2018
Book
Simulation and Optimization of Digital Circuits

Print ISBN: 978-3-319-71636-7

Electronic ISBN: 978-3-319-71637-4

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-3-319-71637-4_5