Partitioning Strategies in Circuit Simulation

Partitioning strategies are commonly used in network analysis packages for simulating highly integrated circuits such as dynamic memories. These methods allow chip designers to simulate circuits consisting of millions of transistors in reasonable computation time. Using a standard benchmark example, the inverter chain, we consider different approaches used in network analysis to split the system on circuit level. We will show the connection with split numerical methods for ordinary differential equations with partitioned right-hand sides.