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2014 | OriginalPaper | Chapter

7. Photonic Network Architectures III: Advanced Photonic Architectures

Authors : Keren Bergman, Luca P. Carloni, Aleksandr Biberman, Johnnie Chan, Gilbert Hendry

Published in: Photonic Network-on-Chip Design

Publisher: Springer New York

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Abstract

Circuit-switching is a natural use of the photonic transmission medium because it is a simple solution that abstracts many of the physical layer implementation details in network design. However, it can suffer from severe network congestion and starvation when long-lived communication patterns occur. This chapter explores some architectural variations on circuit-switched networks to alleviate some of these issues

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previous chapter Photonic Network Architectures II: Wavelength Arbitration and Routing

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G. Hendry et al., “Silicon nanophotonic network-on-chip using TDM arbitration,” in Proceedings of IEEE Symposium on High-Performance Interconnects, Aug. 2010.

M. Millberg, E. Nilsson, R. Thid, A. Jantsch, “Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip,” in DATE ’04: Proceedings of the conference on Design, automation and test in, Europe, 2004, p. 20890.

K. Goossens, J. Dielissen, and A. Radulescu, “Æthereal network on chip: Concepts, architectures, and implementations,” IEEE Des. Test, vol. 22, no. 5, pp. 414–421, 2005.

M. Schoeberl, “A time-triggered network-on-chip,” in International Conference on Field-Programmable Logic and its Applications (FPL 2007), Aug. 2007, pp. 377–382.

Z. Lu and A. Jantsch, “TDM virtual-circuit configuration for network-on-chip,” IEEE Trans. Very Large Scale Integr. Syst., vol. 16, no. 8, pp. 1021–1034, 2008.

C. Paukovits and H. Kopetz, “Concepts of switching in the time-triggered network-on-chip,” in RTCSA ’08: Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2008, pp. 120–129.

G. Hendry, J. Chan, S. Kamil, L. Oliker, J. Shalf, L. Carloni, and K. Bergman, “Silicon nanophotonic network-on-chip using TDM arbitration,” in 2010 IEEE 18th Annual Symposium on High Performance Interconnects (HOTI), Aug. 2010, pp. 88–95.

A. Edman and C. Svensson, “Timing closure through a globally synchronous, timing partitioned design methodology,” in DAC ’04: Proceedings of the 41st annual Design Automation Conference, 2004, pp. 71–74.

J.-F. Zheng, F. Robertson, E. Mohammad, I. Young, D. Ahn, K. Wada, J. Michel, L. Kimerling, “On-chip optical clocking signal distribution,” in Optics in Computing, 2003, p. OWB3.

10.

G. Hendry, E. Robinson, V. Gleyzer, J. Chan, L. P. Carloni, N. Bliss, and K. Bergman., “Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors.” Journal of Parallel and Distributed Computing, Jan. 2011.

11.

G. Roelkens, D. V. Thourhout, and R. Baets, “Continuous-wave lasing from DVS-BCB heterogeneously integrated laser diodes,” in Integrated Photonics and Nanophotonics Research and Applications, 2007, p. ITuG4.

12.

G. Hendry, S. Kamil, A. Biberman, J. Chan, B. G. Lee, M. Mohiyuddin, A. Jain, K. Bergman, L. P. Carloni, J. Kubiatowicz, L. Oliker, and J. Shalf, “Analysis of photonic networks for a chip multiprocessor using scientific applications,” in Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, ser. NOCS ’09, May 2009, pp. 104–113.

13.

J. Chan and K. Bergman, “Photonic interconnection network architectures using wavelength-selective spatial routing for chip-scale communications,” Optical Communications and Networking, IEEE/OSA Journal of, vol. 4, no. 3, pp. 189–201, Mar. 2012.

14.

J. Chan, N. Ophir, C. P. Lai, A. Biberman, H. L. R. Lira, M. Lipson, and K. Bergman, “Data transmission using wavelength-selective spatial routing for photonic interconnection networks,” Optical Fiber Communication Conference, Mar. 2011.

15.

K. Preston, N. Sherwood-Droz, J. Levy, and M. Lipson, “Performance guidelines for WDM interconnects based on silicon microring resonators,” in Lasers and Electro-Optics (CLEO), 2011 Conference on, May 2011.

16.

B. Lee, A. Biberman, P. Dong, M. Lipson, and K. Bergman, “All-optical comb switch for multiwavelength message routing in silicon photonic networks,” IEEE Photonics Technology Letters, vol. 20, no. 10, pp. 767–769, May 2008.

17.

Q. Xu, D. Fattal, and R. G. Beausoleil, “Silicon microring resonators with 1.5-\(\upmu \)m radius,” Opt. Express, vol. 16, no. 6, pp. 4309–4315, Mar. 2008.

18.

A. Shacham, K. Bergman, and L. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Transactions on Computers, vol. 57, no. 9, pp. 1246–1260, Sep. 2008.

19.

S. Koohi, M. Abdollahi, and S. Hessabi, “All-optical wavelength-routed NoC based on a novel hierarchical topology,” in Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on, May 2011, pp. 97–104.

20.

X. Yuan, R. Melhem, and R. Gupta, “Distributed path reservation algorithms for multiplexed all-optical interconnection networks,” Computers, IEEE Transactions on, vol. 48, no. 12, pp. 1355–1363, Dec. 1999.

21.

F. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nature Photonics, vol. 1, pp. 65–71, 2006.

22.

W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides,” OSA Optics Letters, vol. 32, no. 19, pp. 2801–2803, 2007.

23.

S. Assefa, B. G. Lee, C. Schow, W. M. Green, A. Rylyakov, R. A. John, and Y. A. Vlasov, “20 Gbps receiver based on germanium photodetector hybrid-integrated with 90 nm CMOS amplifier,” in in CLEO:2011 - Laser Applications to Photonic Applications, 2011, p. PDPB11.

24.

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors,” J. Emerg. Technol. Comput. Syst., vol. 7, no. 2, pp. 7:1–7:25, Jul. 2011.

25.

J. Chan, G. Hendry, A. Biberman, and K. Bergman, “Architectural exploration of chip-scale photonic interconnection network designs using physical-layer analysis,” IEEE/OSA Journal of Lightwave Technology, vol. 28, no. 9, pp. 1305–1315, May 2010.

Title: Photonic Network Architectures III: Advanced Photonic Architectures
Authors: Keren Bergman
Luca P. Carloni
Aleksandr Biberman
Johnnie Chan
Gilbert Hendry
Publisher: Springer New York
Book: Photonic Network-on-Chip Design
Print ISBN: 978-1-4419-9334-2

Electronic ISBN: 978-1-4419-9335-9

Copyright Year: 2014
DOI: https://doi.org/10.1007/978-1-4419-9335-9_7