Power Mitigation in High-Performance 32-Bit MIPS-Based CPU on Xilinx FPGAs

The aim of this paper is, to introduce design of a 32-bit MIPS (Microprocessor Interlocked Pipeline Stages) based processor containing five stages of pipeline, to incorporate power optimization techniques for FPGAs. The functionality of this design has been verified by writing Verilog Modules on Xilinx 14.5 selecting the target FPGA device. The design helps to improve the speed and increase the whole throughput of the processor. Synthesis and simulation results have been taken from ModelSim 6.2c. Analysis the design floorplan of 32-bit CPU and study of the detailed netlist has been performed on PlanAhead tool, which was giving accurate results. From the performance viewpoint, FPGA-based implementation of processor is totally centered on the designing of processor architectures in Verilog HDL and increasing the overall speedup with power mitigation at Spartan class (45 nm and 90 nm) FPGAs. The significant features of this work are; increased number of instructions, enhanced performance and low power consumption with HDL modification techniques. The design has 5 levels of logic and delay of 14.202 ns with the maximum frequency of operation at 70.413 MHz for Spartan-6. Optimized power observed was about 22.72% after applying power reduction techniques, which make this work useful for low power FPGAs.