Reliability evaluation of a novel fault tolerant multilevel inverter with reduced components

Preserving the reliability and continuity of dc-ac converters, fault-related issues are important and challenging subjects in industrial processes and energy systems. Owing to this fact based on power converters, nowadays fault tolerant structures are designed in such a way that reliability improvement and system availability would be given the highest priority. Multilevel inverters (MLIs) are a versatile and high-performance power electronic converter which is popular in medium voltage to high power applications for their unique characteristics. A power electronic converter is used in many research, academic, and industrial applications—for example, in HVDC, renewable energy systems, adjustable speed drives, hybrid electric vehicles, AC motor drives, diversification of solar energy, and unified power quality correction and so on [1]. Moreover, the reliability of the whole converter system is in the challenge as widespread and increasing demand in various applications. MLIs are more popular than two-level inverters because of their advantages such as their capability to have medium voltage to high power output, low harmonic contents, less common mode voltage and lower dv/dt stress on load, reduction in filter size, wide range of power operation, better electromagnetic compatibility, reduced voltage stress on switches, draws input current with low distortion, less switching losses and higher efficiency.

The basic configurations of inverters commercially available are neutral point clamped (NPC) or diode clamped, flying capacitor (FC) or capacitor clamped and cascaded H-bridge (CHB) converters. One of the most widely used converters is CHB due to its modular design. Complex circuitry, reduction in efficiency and low reliability are the major complications in these basic inverters as the number of levels increased.

According to a survey on multilevel converter topologies, it is concluded that all these topologies encounter an increased number of component count and require huge capacitors leading to sophisticated control techniques [2]. In the current scenario, advancement in inverter circuits which can meet the issues above is greatly recommended. To overcome these drawbacks, a new breed of MLI topologies is developed with reduced component (RC) and improved performance to further advancement in converters.

RC-MLIs offer significant advantages over conventional converters such as a minimum number of switches requirement, protection circuit and heat sink, fewer diodes as the number of output level increases. Hence, results in low cost, reduced circuit complexity and reduced weight to RC-MLIs. Each of these has its pros and cons proposed in various literature [3, 4]. Due to the significant upswing in voltage levels with a reduction in power switches, RC MLIs can be considered as a good alternative for converters to be used in power applications. However, comparing with other inverter structures containing a large number of components, MLIs have lower reliability resulting in a higher possibility of malfunctioning. Anyone of the single open switch fault (OSF) may cause abnormal operation of the electrical drive systems. Practically, open circuit and short circuit faults are associated with the types of faults arises in the power switches. The system is fatally damaged when a power switch experiences a short circuit and requires extra circuitry to safeguard. To analyse open circuit faults in power switches, this work considers open circuit faults in power switches. In case of RC-MLIs lowering the components tend to a reduction in redundant states that means any device failure directly affects the whole system interruption. In recent years, a new pace in topologies design has been attracting attention with the specific objective of reducing component counts. An improved voltage waveform can be obtained by adding more levels at the output [5]. Moreover, reduction in device count is achieved, but certain features such as reduction in several switching states and loss of control complexity can be affected. As a result, many RC-MLIs suffered from lack of charge balance control, incapable of sustaining in fault scenarios. Additionally, preserving an aspect of redundant states is being actively pursued in addition to reducing device count.

Fault tolerant solutions are presented by several investigators to commercially available MLIs (NPC, FC, and CHB) with multilevel voltage output [6]. In recent times, the issues related to failures in MLIs are getting attention of investigators. These concerns are to be resolved to fulfill the operational requirements of the system. The subject of reliability in MLIs is prevalent as they have a more significant number of devices resulting in a high probability of fault occurrence. The main reason behind overall inverter failure is the failure of active power semiconductor devices, drivers, and sources [7, 8]. Due to the large number of components used in converters, it is always possible for an open circuit fault to occur concurrently at one or more components. Therefore, it is required to stop the operation of the system to prevent damage. Additionally, it may be possible to provide continuous power supply to the load and tolerate open circuit faults in order to maintain an acceptable output voltage.

Various FT topologies are proposed to address the reliability issue in DC-AC converters [9]. The main disadvantage of traditional two-level inverters is their low reliability; they are being replaced by MLIs. An increase in switching devices and their vulnerability leads to this issue [10]. A bidirectional switch or relay is connected to CHB inverter to isolate the faulted cell from the primary system [11]. NPC structure is made FT with the use of switching elements in place of the clamping diodes [12]. Bidirectional switches are included in the modified NPC 3-Φ structure [13]. A hybrid structure is proposed in [14] by combining one leg of a diode-clamped inverter with a half bridge and the addition of a bidirectional switch. This structure is capable of tolerating faults in case of switch/source failure along with equal power sharing, thereby increasing the overall number of device count and cost of the inverter. In [15, 16], FT structure of FC is presented. Although, the circuit itself has capability of fault ride through, however, the major issues of concern are increase in devices and complexity in capacitor balancing technique. In case of short circuit faults in switches, additional circuitry is required to protect the inverter as they are catastrophic faults [17].

A brief review is included in [18, 19] regarding the operation and control of MLIs with reduced components. According to a survey presented in [20], 21% and 13% MLIs being used in several industrial appliances are found to be prone to the power switch and soldering failures, respectively. Thus, an overall failure of 34% of the device module can be observed leading to whole system dysfunction. Another study shows a total of 38% of variable speed ac drives malfunction due to power switch failure [21]. A study mentioned in [22‐24] examined the switching device failure rate and reliability of MLI configurations. From the past literature, several solutions that are found to meet fault tolerant operation are discussed in [22, 25‐29]. In general, power electronic converters are divided into four categories based on their fault tolerance capability and depending upon hardware redundancy as depicted in Fig. 1. This study is confined to a switch-level fault, i.e. OSF in the proposed novel reduced components dc-ac converter.

The overall system can shut down and take a longer time to get back to normal after failure of any single/multiple device in RC-MLIs, despite the reduction in semiconductor device count. These limitations bring the need for fault tolerance strategy to the affected systems to maintain its operation continuously by supplying power to the load. Hence, in this paper, a FT RC-MLI structure is proposed. RC-MLIs are compromising itself in terms of redundant states and therefore, OSF may cost substantial loss by system interruption. The proposed FT structure generates required redundant states (RS). The redundant states play a strategic role in case of switch level fault occurrence. The stated paper fills the gap by developing novel fault tolerant RC-MLI.

A single phase form of the proposed FT-MLI is presented in this work to address earlier discussed subjects of concern. To make it more reliable and fault-tolerant, the least changes in the switching pattern is accomplished. The minimum probability of possible power device failure is given in tabulation of the presented FT-MLI. In the event of OSF, the minimum levels required to maintain the functionality of the systems with acceptable output voltage levels are generated. A sufficient number of desired redundancy can be generated by the proposed FT-MLI. It confirms the continuation of operation of the structures in instance of OSF. A brief discussion is presented in the next section. A comparative study based on the component count, FT feature and reliability analysis are presented for the proposed FT-MLI with some recently published structures. Detection and identification of faults are not covered and kept out of the scope of this research work. Figure 2 shows a flow chart in relation to working of fault tolerant operation of proposed MLI in the event of OSF.

In this section, the proposed FT-MLI is briefly analysed based on their various combination of ON state switches and evaluated accordingly to sustain faults in one of the switches. The single phase form of the proposed FT structure is outlined for simplicity of operation.

To authenticate the performance of the proposed FT concept, the newly developed single phase FT-MLI is simulated using MATLAB/SIMULINK along with Sim-Power-Systems toolbox. The arbitrarily considered inverter parameters for the proposed FT topology are mentioned in Table 5. The proposed FT topology is controlled by a multicarrier pulse width modulation strategy. The generation of switching pulses is governed by continuous comparison of carrier signals (3000 Hz) and fundamental signal (50 Hz). The triggering pulses so obtained are employed to each an individual switches to achieve different voltage levels. The number of carrier signals proportionally increases with the increase in levels.

An illustration of the output voltage and current waveform from the proposed FT MVSI is shown in Fig. 7 based on simulations under healthy, faulty and fault cleared conditions. In healthy condition (before t = 0.94 s), the proposed FT structure generates 5-level output voltage with identical voltage steps of 20 V each. For simulation study, an OSF is created at t = 0.94 s to t = 1 s in each of the switch(es), respectively. The state during the period of OSF is known as the faulty state. By the proposed FT control technique, the fault is cleared after t = 1 s and the output voltage waveforms change from unacceptable to acceptable for all switch failures except S₄ and S₆. In case of failure in power switches S₄ and S₆, a five-level output voltage waveform are obtained. It is evident from the above discussion that after the clearance of fault, a full fault-tolerant operation can be achieved when particular power switches S₄ and S₆ fail while failure in other switches as mentioned in Table 2 support partial fault tolerant operation.

Losses associated with the FT-MVSI topology can be analysed and assessed with the use of a thermal modelling simulation performed on the PLECS platform. The PLECS provides a domain for modelling thermal structures and accurately computing switching and conduction losses in switches utilzsing multi-dimensional lookup tables based on manufacturer information or real data. Further, IGBT (GW30NC120HD) switches have been employed as power switches in the PLECS-based simulation model, and the datasheet was imported in order to analyse power losses. The graph showing the steady state displays the loss patterns in Fig. 8. A remarkable total efficiency of 97.40 per cent characterizes the proposed topology. The experimental efficiency of the proposed inverter is 96.94%, which is somewhat less than the simulated efficiency due to losses in the driver units.

To validate the idea of the suggested FT control approach, the proposed FT-MLI is simulated using the MATLAB/SIMULINK software package, and the practical prototype is set up in an experimental setting. The prototype is developed experimentally to ensure that the aforementioned FT structure is feasible. A real-time digital controller, the dSPACE DS1104 is used for the generation of the switching pulses. A host-PC operating the MATLAB/Simulink software tool, discrete power IGBT modules with built-in drivers and protection units, DC sources, a dSPACE1104 controller, a power quality analyzer (Fluke 43B), and a digital storage oscilloscope are all employed in the experimental setup. YOKOGAWA DL750E scope-coder is used to measure and record all the waveforms. Figure 9 shows the laboratory picture of the experimental setup.

In order to verify the proposed FT MVSI structure experimentally, a pre-programmed open circuit fault is created after t = 0.94 s on different switches and cleared at t = 1 s. In the duration of t = 0.94 s to t = 1 s, an unacceptable waveform is observed for individual switches. Figure 10a, b shows the transition of output voltage waveform from five to three level after fault inception. A partial fault-tolerant solution with reduced magnitude of voltage and current is observed for the proposed FT structure. Figure 10c shows the full fault-tolerant solution to the proposed FT structure.

The similar switch failures have been investigated in a simulation study, and the same results are observed. It is worth to note that the simulated and experimented results are identical to each other. Finally, the proposed FT-MLI structure is validated satisfactorily. The proposed FT MVSI is claimed to be reduced components FT-MLI. One of the key outcomes of presented studies is the continuous operation of proposed FT-MLI by adopting the proposed FT switching scheme in spite of the occurrence of OSF.

Also, the proposed topology is tested for THD under RL load which results in a good performance. Under this condition, the recorded output voltage and load current THD are 7.8% and 1.4% under healthy (before open-circuit fault) condition as illustrated in Fig. 11a, b, respectively.

Similarly, the proposed topology is tested for THD under a fault cleared state. Under this condition, the recorded output voltage and load current THD are 19.6% and 13.6% under fault cleared (after OC fault) condition as illustrated in Fig. 12a, b, respectively.

Notably, the value of THD can be increased by 5%, either by increasing the number of levels at the output or by increasing the switching frequency, although with the limitations of increased switching losses and reduced efficiency.

To illustrate the merits of proposed FT-MVSI, an appropriate comparison is carried out with classical and recently published MLIs. Table 6 summarizes the stated comparison. The comparison shows that the proposed FT structure requires fewer components for its reliable operation. While the structures in [14, 25, 28] and NPC comprise extra circuitry like clamping diodes which increase component count, whereas NPC does not possess FT operation. The proposed FT-MLI is highly competent to CHB along with minimum switch count. The structures in [22, 26, 27, 29] have higher switch count with FT ability in case of single OSF and unable to produce output voltage in case of multiple swich failure. The FT-MLI [28] requires more switches and highly competent to presented FT-MVSI in the event of multi switch failure scenario. Furthermore, four switches are conducting at an instant to generate a level in CHB, but in the proposed one, the conducting switches simultaneously (two) are less.

Reliability, continuity and fault related subjects in industries have been studied for decades and MLIs have become a key part in number of industry applications in which failures can have theatrical effects. An accident or fault in factory and industries can create vast economic and social losses. This research represents an approach to introducing fault-tolerant operation of single-phase MLI by considering either switch-open or multi-switch-open situation. The article has underlined the importance of the operation of the proposed FT structure even after OSF by providing continuous supply to the load with acceptable output voltage waveform. Simulation is used to prove the proposed concept, and experimental tests are used to verify the results. The obtained results prove the reliable operation of FT MVSI which can be achieved through the proposed FT control strategy. The current study has investigated for a MLI structure having symmetrical sources only. In addition to ensure fault tolerant operation in the event of a fault occurence in a single switch, the proposed fault tolerant strategy ensures fault tolerant operation in multiple switches as well. The proposed structure can be maintained at the rated voltage by using the step-up transformers in a faulty scenario.