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Published in:
Anatomy of the Focal-Plane Sensor-Processor Arrays Read chapter Read first chapter

2011 | OriginalPaper | Chapter

SCAMP-3: A Vision Chip with SIMD Current-Mode Analogue Processor Array

Author : Piotr Dudek

Published in: Focal-Plane Sensor-Processor Chips

Publisher: Springer New York

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Abstract

In this chapter, the architecture, design and implementation of a vision chip with general-purpose programmable pixel-parallel cellular processor array, operating in single instruction multiple data (SIMD) mode is presented. The SIMD concurrent processor architecture is ideally suited to implementing low-level image processing algorithms. The datapath components (registers, I/O, arithmetic unit) of the processing elements of the array are built using switched-current circuits. The combination of a straightforward SIMD programming model, with digital microprocessor-like control and analogue datapath, produces an easy-to-use, flexible system, with high-degree of programmability, and efficient, low-power, small-footprint, circuit implementation. The SCAMP-3 chip integrates 128 ×128 pixel-processors and a flexible read-out circuitry, while the control system is fully digital, and currently implemented off-chip. The device implements low-level image processing algorithms on the focal plane, with a peak performance of more than 20 GOPS, and power consumption below 240mW.

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previous chapter Anatomy of the Focal-Plane Sensor-Processor Arrays
next chapter MIPA4k: Mixed-Mode Cellular Processor Array
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Metadata
Title
SCAMP-3: A Vision Chip with SIMD Current-Mode Analogue Processor Array
Author
Piotr Dudek
Copyright Year
2011
Publisher
Springer New York
Book
Focal-Plane Sensor-Processor Chips

Print ISBN: 978-1-4419-6474-8

Electronic ISBN: 978-1-4419-6475-5

Copyright Year: 2011

DOI
https://doi.org/10.1007/978-1-4419-6475-5_2