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Published in:
2019 | OriginalPaper | Chapter
3. Simulation of VHDL Programs
Author : Orhan Gazi
Published in: A Tutorial Introduction to VHDL Programming
Publisher: Springer Singapore
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Abstract
In this chapter we will give information about the simulation of VHDL programs. Once we implement a digital circuit or an algorithm in VHDL language, we need to check the correctness of the implementation. For this purpose, we write test programs which are used to supply values to the input ports of the VHDL program, and it is possible to observe the values at the output ports. The test program written to simulate the input and output behavior of the VHDL programs is usually called test-bench.