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2016 | OriginalPaper | Chapter

1. Steep Slope Devices and TFETs

Authors : Lining Zhang, Jun Huang, Mansun Chan

Published in: Tunneling Field Effect Transistor Technology

Publisher: Springer International Publishing

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Abstract

Reducing energy dissipations per function with the integrated circuit (IC) chips is always an appealing research topic. Techniques in the fundamental electronic device levels are being pursued besides of those in the architecture level. In this chapter, we introduce several device candidates with a common feature of steep slope as possible solutions for lower power computations. The ever increasing power densities with the complementary metal-oxide-semiconductor (CMOS) technologies and the behind reasons are reviewed first. Implications are reached that a device with steep slopes beyond the Boltzmann limitations helps. Then, several devices realizing steep slopes beyond that of the MOS field-effect-transistor (FET) technology are introduced, including the impact ionization FETs, the electro-mechanical FETs, the piezoelectric transistor, the ferroelectric FETs, the feedback FETs, and the tunneling FETs (TFETs). Afterward, we analyze the key features of the basic TFET operations and characteristics in details. Finally, several widely studied performance boosters for the TFET technology are also reviewed from device structures to doping and material engineering.

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S. Borkar, Low power design challenges for the decade. in Proceedings of ASP-DAC, pp. 293–296, 2001

P. Huber, Dig more coal—the PCs are coming. Forbes, pp. 70–72, May 1999

M. Mills, Opportunity in the Internet’s voracious energy appetite: the cloud begin with coal. Forbes, 31 May 2011

R.W. Keyes, R. Landauer, Minimal energy dissipation in logic. IBM J. Res. Dev. 14, 152–157 (1970)CrossRef

J.D. Meindl, J.A. Davis, The fundamental limit on binary switching energy for terascale integration. IEEE J. Solid-State Cir. 35(10), 1515–1516 (2000)CrossRef

R.W. Keyes, Fundamental limits of silicon technology. Proc. IEEE 89, 227–239 (2001)CrossRef

K.L. Wang, K. Galatsis, R. Ostroumov, A. Khitun, Z. Zhao, S. Han, Nanoarchitectonics for hetero-geneous integrated nanosystems. Proc. IEEE 96(2), 212–229 (2008)CrossRef

R. Dennard, F.H. Gaensslen, H. Yu, V. Rideout, E. Bassous, A.R. Leblanc, Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circuits sc-9, 256–268 (1974)

P. Packan, Device and circuit interactions. IEEE IEDM Short Course (2007)

10.

E.J. Nowak, Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J. Res. Dev. 46, 169–180 (2002)CrossRef

11.

M. Bohr, S. Ahmed, L. Brigham, R. Chau, R. Gasser, R. Green, W. Hargrove, E. Lee, R. Natter, S. Thompson, K. Weldon, S. Yang, A high performance 0.35 μm logic technology for 3.3 V and 2.5 V operation. IEDM Tech. Dig. 273–276 (1994)

12.

M. Bohr, S.S. Ahmed, S.U. Ahmed, M. Bost, T. Ghani, J. Greason, R. Hainsey, C. Jan, P. Packan, S. Sivakumar, S. Thompson, J. Tsai, S. Yang, A high performance 0.25 μm logic technology optimized for 1.8 V operation. IEDM Tech. Dig. 847–850 (1996)

13.

S. Yang, S. Ahmed, B. Arcot, R. Arghavani, P. Bai, S. Chambers, P. Charvat, R. Cotner, R. Gasser, T. Ghani, M. Hussein, C. Jan, C. Kardas, J. Maiz, P. McGregor, B. McIntyre, P. Nguyen, P. Packan, I. Post, S. Sivakumar, J. Steigerwald, M. Taylor, B. Tufts, S. Tyagi, M. Bohr, A high performance 180 nm generation logic technology. IEDM Tech. Dig. 197–200 (1998)

14.

S. Tyagi, M. Alavi, R. Bigwood, T. Bramblett, J. Brandenburg, W. Chen, B. Crew, M. Hussein, P. Jacob, C. Kenyon, C. Lo, B. Mcintyre, Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, S. Thompson, B. Tufts, J. Xu, S. Yang, M. Bohr, A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects. IEDM Tech. Dig. 567–570 (2000)

15.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, M. Bohr, A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. IEDM Tech. Dig. 978–980 (2003)

16.

P. Bai, C. Auth, S. Lalakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastina, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, M. Bohr, A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm² SRAM cell. IEDM Tech. Dig. 657–660 (2004)

17.

K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. james, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. Mcintyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki, A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100 % Pb-free packaging. IEDM Tech. Dig. 247–250 (2007)

18.

P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, J. Jopling, C. Kenyon, S-H. Lee, M. Liu, S. Lodha, B. Mattis, A. Murthy, L. Neiberg, J. Neirynck, S. Pae, C. Parker, L. Pipes, J. Sebastian, J. Seiple, B. Sell, A. Sharma, S. Sivakumar, B. Song, A. St. Amour, K. Tone, T. Troeger, C. Weber, K. Zhang, Y. Luo, S. Natarajan, High performance 32 nm logic technology featuring 2nd generation high-k + metal gate transistors. IEDM Tech. Dig. 659–662 (2009)

19.

C.-H. Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, W. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, J. Park, K. Phoa, A. Rahman, C. Staus, H. Tashiro, C. Tsai, P. Vandervoorn, L. Yang, J.-Y. Yeh, P. Bai, A 22 nm Soc platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultralow power, high performance and high density SoC applications. IEDM Tech. Dig. 44–47 (2012)

20.

S. Natarajan, M. Agostinelli, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu, T. Ghani, M. Giles, S. Govindaraju, R. Grover, W. Han, D. Hanken, E. Haralson, M. Haran, M. Heckscher, R. Heussner, P. Jain, R. James, R. Jhaveri, I. Jin, H. Kam, E. Karl, C. Kenyon, M. Liu, Y. Luo, R. Mehandru, S. Morarka, L. Neiberg, P. Packan, A. Paliwal, C. Parker, P. Patel, R. Patel, C. Pelto, L. Pipes, P. Plekhanov, M. Prince, S. Rajamani, J. Sandford, B. Sell, S. Sivakumar, P. Smith, B. Song, K. Tone, T. Troeger, J. Wiedemer, M. Yang, K. Zhang, A 14 nm logic technology featuring 2nd generation FinFET transistors, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm² SRAM cell size. IEDM Tech. Dig. 71–74 (2014)

21.

R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, M. Radosavljevic, Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Tran. Nanotechnology 4(2), 153–158 (2005)CrossRef

22.

S.M. Sze, Physics of Semiconductor Devices, 2nd edition (John Wiley & Sons, 1981)

23.

K. Gopalakrishnan, P.B. Griffin, J.D. Plummer, I-MOS: a novel semiconductor device with a sub-threshold slope lower than kT/q. IEDM Tech. Dig. 289–292 (2002)

24.

D. Sarkar, N. Singh, K. Banerjee, A novel enhanced electric-field impact-ionization MOS transistor. IEEE Electron Dev. Lett. 31(11), 1175–1177 (2010)

25.

E. Toh, G. Wang, L. Chan, G. Lo, G. Samudra, Y. Yeo, Strain and materials engineering for the I-MOS transistor with an elevated impact-ionization region. IEEE Trans. Electron Dev. 54(10), 2778–2785 (2007)CrossRef

26.

A.M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M.J. Declercq, P. Renaud, C. Hibert, P. Fluckiger, G. Racine, Modeling and design of a low-voltage SOI suspended-gate MOSFET with a metal-over-gate architecture. Proc. ISQED 496–501 (2002)

27.

H. Kam, D. Lee, R. Howe, T.J. King, A new nano-electro-mechanical field-effect transistor design for low power electronics. IEDM Tech. Dig. 464–466 (2005)

28.

N. Abele, R. Fritschi, K. Boucart, F. Casset, P. Ancey, A. M. Ionescu, Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor. IEDM Tech. Dig. 479–481 (2005)

29.

T.J. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott, E. Alon, Prospects for MEM logic switch technology. IEDM Tech. Dig. 424–427 (2014)

30.

N. Xu, J. Sun, I. Chen, L. Hutin, Y. Chen, J. Fujiki, C. Qian, T.J. King Liu, Hybrid CMOS/BEOL-NEMS technology for ultra-low-power IC applications. IEDM Tech. Dig. 677–680 (2014)

31.

D. Newns, G. Martyna, B. Elmegreen, X. Liu, T. Theis, Extended abstract, in Proceedings of the 15th US-Japan Seminar on Dielectric and Piezoelectric Ceramics, Castle Park Hotel, Kagoshima, Japan, 6–9 Nov 2011

32.

P. Solomon, B. Bryce, M. Kuroda, R. Keech, S. Shetty, T. Shaw, M. Copel, L. Hung, A. Schrott, C. Armstrong, M. Gordon, K. Reuter, T. Theis, W. haensch, S. Rossnagel, H. Miyazoe, B. Elmegreen, X. Liu, S. Trolier-Mckinstry, G. Martyna, D. Newns, Pathway to the piezoelectric transduction logic device. Nano Lett. 15, 2391–2395 (2015)CrossRef

33.

S. Salahuddin, S. Datta, Can the subthreshold swing in a classical FET be lowered below 60 mV/dec? IEDM Tech. Dig. 1–4 (2008)

34.

S. Salahuddin, S. Datta, Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008)CrossRef

35.

G. Salvatore, D. Bouvet, A.M. Ionescu, Demonstration of subthreshold swing smaller than 60 mV/ dec in Fe-FET with P(VDF-TrFE)/SiO₂ gate stack. IEDM Tech. Dig. 1–4 (2011)

36.

A. Padilla, C. Yeung, C. Shin, C. Hu, T.J. King Liu, Feedback FET: a novel transistor exhibiting steep switching behavior at low bias voltages. IEDM Tech. Dig. 171–174 (2008)

37.

Q. Zhou, S. Huang, H. Chen, C. Zhou, Z. Feng, S. Cai, K.J. Chen, Schottky source/drain Al₂O₃/InAlN/ GaN MIS-HEMT with steep sub-threshold swing and high on/off current ratio. IEDM Tech. Dig. 777–780 (2011)

38.

C. Yeung, A. Padilla, T.J. King Liu, C. Hu, Programming characteristics of the steep turn-on/off feedback FET. VLSI Tech. Dig. 176–177 (2009)

39.

Z. Lu, N. Collaert, M. Aoulaiche, B. De Wachter, A. De Keersgieter, J.G. Fossum, L. Altimime, M. Jurczak, Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages. IEDM Tech. Dig. 407–410 (2010)

40.

J. Zhang, M. De Marchi, P. Gaillardon, G. De Micheli, A schottky-barrier silicon FinFET with 6.0 mV/ dec subthreshold slope over 5 decades of current. IEDM Tech. Dig. 339–342 (2014)

41.

E.O. Kane, Theory of tunneling. J. Appl. Phys. 32(1), 83–91 (1961)MathSciNetCrossRefMATH

42.

F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, S. Deleonibus, Impact of SOI, Si_1−xGe_xOI and GeOI substrates on CMOS compatible tunnel FET performance. IEDM Tech. Dig. 163–166 (2008)

43.

K. Jeon, W.-Y. Loh, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C.S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. K. Liu, C. Hu, Si tunnel transistors with a novel silicided source and 46 mV/dec swing. VLSI Tech. Dig. 121–122 (2010)

44.

W.Y. Choi, B.-G. Park, J.D. Lee, T.-J.K. Liu, Tunneling field effect transistors with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)CrossRef

45.

R. Gandhi, Z. Chen, N. Singh, K. Banerjee, S. Lee, Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤ 50 mV/decade) at room temperature. IEEE Electron Device Lett. 32(4), 437–439 (2011)CrossRef

46.

Q. Shi, L. Zhang, Y. Zhu, L. Liu, M. Chan, H. Guo, Atomic disorder scattering in emerging transistors by parameter free first principle modeling. IEDM Tech. Dig. 733–736 (2014)

47.

S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K.K. Bourdelle, Q.T. Zhao, S. Mantl, Ω-gated silicon and strain silicon nanowire array tunneling FETs. IEEE Electron Device Lett. 33(11), 1535–1537 (2012)CrossRef

48.

Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambridge, 1998)

49.

L. Zhang, J. He, M. Chan, A Compact Model for Double-Gate Tunneling Field-Effect-Transistors and Its Implications on Circuit Behaviors. IEDM Tech. Dig. 143–146 (2012)

50.

V. Nagavarapu, R. Jhaveri, J.C.S. Woo, The tunnel source (pnpn) n-MOSFET: a novel high perform-ance transistor. IEEE Trans. Electron Dev. 55(4), 1013–1019 (2008)CrossRef

51.

A. Tura, Z. Zhang, P. Liu, Y. Xie, J.C.S. Woo, Vertical silicon p-n-p-n tunnel nMOSFET with MBE-grown tunneling junction. IEEE Trans. Electron Dev. 58(7), 1907–1913 (2011)CrossRef

52.

C. Hu, P. Patel, A. Bowonder, K. Jeon, S. Kim, W. Loh, C. Kang, J. Oh, P. Majhi, A. Javey, T.S. King Liu, R. Jammy, Prospect of tunneling green transistor for 0.1 V CMOS. IEDM Tech. Dig. 387–390 (2010)

53.

H. Flietner, The E(k) relation for a two-band scheme of semiconductors and the application to the metal-semiconductor contact. Phys. Stat. Sol. 54, 201–208 (1972)CrossRef

54.

S. Kim, H. Kam, C. Hu, T.J. King Liu, Germanium-source tunnel field-effect transistors with record high I_on/I_off. VLSI Tech. Dig. 178–179 (2009)

55.

M. Luisier, G. Klimeck, Atomistic full-band design study of InAs band-to-band tunneling field-effect transistors. IEEE Electron Device Lett. 30(6), 602–604 (2009)CrossRef

56.

H. Zhao, Y. Chen, Y. Wang, F. Zhou, F. Xue, J. Lee, In_0.7Ga_0.3As tunneling field-effect transistors with an Ion of 50 μA/μm and a subthreshold Sswing of 86 mV/dec using HfO₂ gate oxide. IEEE Electron Device Lett. 31, 1392–1394 (2010)CrossRef

57.

S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallett, A. Ali, T. Mayer, V. Narayanan, D. Schlom, A. Liu, S. Datta, Experimental demonstration of 100 nm channel length In_0.53Ga_0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultralow-power logic and SRAM applications. IEDM Tech. Dig. 949–952 (2009)

58.

Y. Lu, G. Zhou, R. Li, Q. Liu, Q. Zhang, T. Vasen, S. Chae, T. Kosel, M. Wistey, H. Xing, A. Seabaugh, P. Fay, Performance of AlGaSb/InAs TFETs with gate electric field and tunneling direction aligned. IEEE Electron Device Lett. 33(5), 655–657 (2012)CrossRef

59.

R. Li, Y. Lu, G. Zhou, Q. Liu, S. Chae, T. Vasen, W. Hwang, Q. Zhang, P. Fay, T. Kosel, M. Wistey, H. Xing, A. Seabaugh, AlGaSb/InAs tunnel field-effect transistor with on-current of 78 μA/μm at 0.5 V. IEEE Electron Device Lett. 33(3), 363–365 (2012)CrossRef

60.

D. Mohata, R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, V. Narayanan, J. Fastenau, D. Loubychev, A. Liu, S. Datta, Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered heterojunctions for 300 mV logic applications. IEDM Tech. Dig. 781–784 (2011)

61.

G. Dewey, B.C. Kung, J. Boardman, J.M. Fastenau, J. Kavalieros, R. Kotlyar, W.K. Liu, D. Lubyshev, M. Metz, N. Mukherjee, P. Oakey, R. Pillarisetty, M. Radosavljevic, H. Then, R. Chau, Fabrication, characterization, and physics of III-V heterojunction tunneling field effect transistors for steep sub-threshold swing. IEDM Tech. Dig. 785–788 (2011)

62.

K. Tomioka, M. Yoshimura, T. Fukui, Steep-slope tunnel field-effect transistors using III-V nanowire/ Si heterojunction. VLSI Tech. Dig. 47–48 (2012)

63.

K. Moselund, H. Schmid, C. Bessire, M. Bjork, H. Ghoneim, H. Riel, InAs-Si nanowire heterojunction tunnel FETs. IEEE Electron Device Lett. 33(10), 1453–1455 (2012)CrossRef

64.

H. Riel, K. Moselund, C. Bessire, M.T. Bjork, A. Schenk, H. Ghoneim, H. Schmid, InAs/Si heterojunc-tion nanowire tunnel diodes and tunnel FETs. IEDM Tech. Dig. 391–394 (2012)

65.

M. Kim, Y. Wakabayashi, R. Nakane, M. Yokoyama, M. Takenaka, S. Takagi, High I_on/I_off Ge-source ultrathin body strained-SOI tunnel FETs. IEDM Tech. Dig. 331–334 (2014)

66.

J. Smith, S. Das, J. Appenzeller, Broken-gap tunnel MOSFET: a constant-slope sub-60 mV/dec transistor. IEEE Electron Device Lett. 32(10), 1367–1369 (2011)CrossRef

67.

L. Register, M. Hasan, S. Banerjee, Stepped broken-gap heterobarrier tunneling field-effect transistor for ultralow power and high speed. IEEE Electron Device Lett. 32(6), 743–745 (2011)CrossRef

68.

M. Luisier, G. Klimeck, Performance comparisons of tunneling field-effect transistors made of InSb, carbon, and GaSb-InAs broken gap heterostructures. IEDM Tech. Dig. 913–916 (2009)

69.

G. Zhou, R. Li, T. Vasen, M. Qi, S. Chae, Y. Lu, Q. Zhang, H. Zhu, J. M. Kuo, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, H. Xing, Novel gate-recessed vertical InAs/GaSb TFETs with record high I_on of 180 μA/μm at V_ds = 0.5 V. IEDM Tech. Dig. 777–780 (2009)

Title: Steep Slope Devices and TFETs
Authors: Lining Zhang
Jun Huang
Mansun Chan
Publisher: Springer International Publishing
Book: Tunneling Field Effect Transistor Technology
Print ISBN: 978-3-319-31651-2

Electronic ISBN: 978-3-319-31653-6

Copyright Year: 2016
DOI: https://doi.org/10.1007/978-3-319-31653-6_1