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2018 | OriginalPaper | Chapter

10. Summary of The Book

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Abstract

In DSAL, contacts (or vias) are indirectly formed through guide patterns (GPs). Thus, the integrity of GP is very important to obtain desirable contacts on a wafer. Since GP is created by traditional lithography, it may have some errors when its shape is large and complex (Shim and Shin, Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC) (2015), Shim, Chung and Shin, Proceedings of the International Conference on Computer Aided Design (2015)) [1, 2], which affect final contact patterns. Such limitation of GP shape calls for careful considerations in physical design. It has been also argued that conventional mask synthesis and verification for traditional lithography are obsolete in DSAL. In this context, this book has addressed problems on physical design and mask synthesis as follows.

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Literature
1.
go back to reference S. Shim, Y. Shin, Physical design and mask optimization for directed self-assembly lithography (DSAL), in Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC) (2015), pp. 80–85 S. Shim, Y. Shin, Physical design and mask optimization for directed self-assembly lithography (DSAL), in Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC) (2015), pp. 80–85
2.
go back to reference S. Shim, W. Chung, Y. Shin, Defect probability of directed self-assembly lithography: fast identification and post-placement optimization, in Proceedings of the International Conference on Computer Aided Design (2015), pp. 404–409 S. Shim, W. Chung, Y. Shin, Defect probability of directed self-assembly lithography: fast identification and post-placement optimization, in Proceedings of the International Conference on Computer Aided Design (2015), pp. 404–409
3.
go back to reference W. Chung, S. Shim, Y. Shin, Redundant via insertion in directed self-assembly lithography, in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (2016), pp. 55–60 W. Chung, S. Shim, Y. Shin, Redundant via insertion in directed self-assembly lithography, in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (2016), pp. 55–60
4.
go back to reference S. Shim, W. Chung, Y. Shin, Placement Optimization for MP-DSAL Compliant Layout, in Proceedings of the International Conference on IC Design and Technology (ICICDT) (2016), pp. 1–4 S. Shim, W. Chung, Y. Shin, Placement Optimization for MP-DSAL Compliant Layout, in Proceedings of the International Conference on IC Design and Technology (ICICDT) (2016), pp. 1–4
5.
go back to reference S. Shim, W. Chung, Y. Shin, Redundant via insertion for multiple-patterning directed-self-assembly lithography, in Proceedings of the Design Automation Conf. (2016), pp. 41:1–41:6 S. Shim, W. Chung, Y. Shin, Redundant via insertion for multiple-patterning directed-self-assembly lithography, in Proceedings of the Design Automation Conf. (2016), pp. 41:1–41:6
6.
go back to reference S. Shim, Y. Shin, Mask optimization for directed self-assembly lithography: inverse DSA and inverse lithography, in Proceedings of the Asia South Pacific Design Automation Conference (2016), pp. 83–88 S. Shim, Y. Shin, Mask optimization for directed self-assembly lithography: inverse DSA and inverse lithography, in Proceedings of the Asia South Pacific Design Automation Conference (2016), pp. 83–88
7.
go back to reference S. Shim, S. Cai, J. Yang, S. Yang, B. Choi, Y. Shin, Verification of directed self-assembly (DSA) guide patterns through machine learning, in Proceedings of the SPIE Advanced Lithography (2015), pp. 1–8 S. Shim, S. Cai, J. Yang, S. Yang, B. Choi, Y. Shin, Verification of directed self-assembly (DSA) guide patterns through machine learning, in Proceedings of the SPIE Advanced Lithography (2015), pp. 1–8
8.
go back to reference S. Shim, Y. Shin, Fast verification of guide patterns for directed self-assembly lithography, in IEEE Transactions on CAD of Integrated Circuits and Systems, to be published S. Shim, Y. Shin, Fast verification of guide patterns for directed self-assembly lithography, in IEEE Transactions on CAD of Integrated Circuits and Systems, to be published
9.
go back to reference W. Ponghiran, S. Shim, Y. Shin, Cut mask optimization for multi-patterning directed self-assembly lithography, in Proceedings of the Design, Automation and Test in Europe (DATE) (2017), pp. 1498–1503 W. Ponghiran, S. Shim, Y. Shin, Cut mask optimization for multi-patterning directed self-assembly lithography, in Proceedings of the Design, Automation and Test in Europe (DATE) (2017), pp. 1498–1503
Metadata
Title
Summary of The Book
Authors
Seongbo Shim
Youngsoo Shin
Copyright Year
2018
DOI
https://doi.org/10.1007/978-3-319-76294-4_10

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