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2018 | OriginalPaper | Chapter

The Design of Reconfigurable Instruction Set Processor Based on ARM Architecture

Authors : Jinyong Yin, Zhenpeng Xu, Xinmo Fang, Xihao Zhou

Published in: Advanced Computer Architecture

Publisher: Springer Singapore

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Abstract

In embedded system, performance and flexibility are two of the most important concerns. To solve the problem of the flexibility of GPP (General Purpose Processor) and the performance of ASIC (Application Specific Integrated Circuit), an ARM based RISP(Reconfigurable Instruction Set Processor) architecture is proposed in this paper which adopts partial reconfiguration and coprocessor mechanism to realize the dynamic online reconfiguration of the processor instruction. A prototype system of the architecture is implemented on Xilinx KC705 FPGA and reconfigurable resource management software is designed and developed for the prototype system. DES encryption/decryption algorithms are tested with prototype, and the test results show that the architecture has the both flexibility of GPP and the performance of ASIC, so it has a wide application prospect.

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Literature
1.
go back to reference Pivezhandi, M., Eshghi, M.: ASIP design for two dimensional cordic based DFT and DCT algorithms. In: 2016 6th International Conference on Computer and Knowledge Engineering (ICCKE), pp. 269–273. Mashhad (2016) Pivezhandi, M., Eshghi, M.: ASIP design for two dimensional cordic based DFT and DCT algorithms. In: 2016 6th International Conference on Computer and Knowledge Engineering (ICCKE), pp. 269–273. Mashhad (2016)
2.
go back to reference Kavitha, V., Ramakrishanan, K.V.: Study of multigrain MRPSoC. In: 2016 3rd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 2534–2538. IEEE, New Delhi (2016) Kavitha, V., Ramakrishanan, K.V.: Study of multigrain MRPSoC. In: 2016 3rd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 2534–2538. IEEE, New Delhi (2016)
3.
go back to reference Hussain, W., Chen, X., Ascheid, G., Nurmi, J.: A reconfigurable application-specific instruction-set processor for fast fourier transform processing. In: 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, pp. 339–345. Washington, DC (2013) Hussain, W., Chen, X., Ascheid, G., Nurmi, J.: A reconfigurable application-specific instruction-set processor for fast fourier transform processing. In: 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, pp. 339–345. Washington, DC (2013)
4.
go back to reference Zhang, B., Mei, K., Zheng, N.: Reconfigurable processor for binary image processing. IEEE Trans. Circuits Syst. for Video Technol. 23(5), 823–831 (2013)CrossRef Zhang, B., Mei, K., Zheng, N.: Reconfigurable processor for binary image processing. IEEE Trans. Circuits Syst. for Video Technol. 23(5), 823–831 (2013)CrossRef
5.
go back to reference Bauer, L., Grudnitsky, A., Damschen, M., Kerekare, S.R., Henkel, J.: Floating point acceleration for stream processing applications in dynamically reconfigurable processors. In: 2015 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), pp. 1–2. Amsterdam (2015) Bauer, L., Grudnitsky, A., Damschen, M., Kerekare, S.R., Henkel, J.: Floating point acceleration for stream processing applications in dynamically reconfigurable processors. In: 2015 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), pp. 1–2. Amsterdam (2015)
6.
go back to reference Chen, X., Minwegen, A., Hussain, S.B., Chattopadhyay, A., Ascheid, G., Leupers, R.: Flexible, efficient multimode MIMO detection by using reconfigurable ASIP. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(10), 2173–2186 (2015)CrossRef Chen, X., Minwegen, A., Hussain, S.B., Chattopadhyay, A., Ascheid, G., Leupers, R.: Flexible, efficient multimode MIMO detection by using reconfigurable ASIP. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(10), 2173–2186 (2015)CrossRef
9.
go back to reference Barat, F., Jayapala, M., de Beeck, P.O., Deconinck, G.: Reconfigurable instruction set processors: an implementation platform for interactive multimedia applications. In: Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 481–485. Pacific Grove, CA, USA (2001) Barat, F., Jayapala, M., de Beeck, P.O., Deconinck, G.: Reconfigurable instruction set processors: an implementation platform for interactive multimedia applications. In: Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 481–485. Pacific Grove, CA, USA (2001)
10.
go back to reference Barat, F., Lauwereins, R., Deconinck, G.: Reconfigurable instruction set processors from a hardware/software perspective. IEEE Trans. Softw. Eng. 28(9), 847–862 (2002)CrossRef Barat, F., Lauwereins, R., Deconinck, G.: Reconfigurable instruction set processors from a hardware/software perspective. IEEE Trans. Softw. Eng. 28(9), 847–862 (2002)CrossRef
Metadata
Title
The Design of Reconfigurable Instruction Set Processor Based on ARM Architecture
Authors
Jinyong Yin
Zhenpeng Xu
Xinmo Fang
Xihao Zhou
Copyright Year
2018
Publisher
Springer Singapore
DOI
https://doi.org/10.1007/978-981-13-2423-9_6