The IoT Physical Layer

Electrocardiogram (ECG) provides valuable information about the heart. By monitoring ECG data, doctors may be able to predict heart problems for swift treatment and better patient outcome. Clinically accepted ECG collection relies on gel-type adhesive electrodes, but to take advantage of increasingly capable home diagnostic systems, robust, comfortable, and affordable dry-type electrodes are desirable. In this chapter, we describe the production and validation of an ECG sensor built from reduced graphene oxide (rGO\(_x\)) -coated nylon fabric. The graphene coating is applied multiple times to optimize the electrical characteristics of the composite fabric. The performance of the new electrode is compared to standard gel-type electrodes.

Weight measurements are part of current medical care for congestive heart failure (CHF) patients. In this chapter, we explore the potential of shoe-mounted pressure sensors to automatically and remotely estimate the weight of CHF patients. We show that weight estimation accuracy degrades due to human subject movement. Moreover, we show that for a standing human subject, the accuracy is influenced by the characteristic of the sensor used to measure pressure. Our experimental evaluation of various pressure sensors widely used in wearable applications reveals that they exhibit properties that are undesirable for precise weight measurements.

Since the first demonstration of an integrated circuit in 1958, the ambitious semiconductor technology has been racing for almost six decades to change the face of the Earth. Moore’s Law and the ‘virtuous cycle’ of investment, scaling and market growth have fueled the sweeping influence that the semiconductor industry now has on every aspect of our everyday lives and the global economic system. Thanks to the striking drop in the cost of computing power, from 5.52 US dollars for a single transistor in 1954 to a billionth of a dollar in 2016, countless human dreams have been realized; from the Apollo missions to the AI and social networking era. While the continued scaling of traditional complementary metal–oxide–semiconductor (CMOS) devices took over the market with its impressive progress, another paradigm of electronics has taken shape: flexible electronics. Instead of focusing on shrinking critical dimensions and reducing power consumption, the growing field of flexible electronics rather aims to leverage compliant form factors and lightweight designs to usher radically novel electronic devices into our lives. Flexible displays, electronic textiles, bio-inspired sensors, and wearable or implantable medical devices, just to name a few, are out-of-reach applications for the rigid form factor of conventional wafer-based electronics. Flexible electronics is more than just a fill-in or an alternative for where conventional electronics fall short. If the integrated circuit was the game changer of the twentieth century, then flexible electronics is the catalyst for the paradigm shift of the twenty-first century.

This chapter covers the physical characterization of various aluminum-doped ZnO films that were synthesized. At high level, it includes electrical characterization followed by mechanical characterization. The electrical characterization includes Hall measurements to assess the mobility of the films, resistance measurements using special microfabricated patterned structures and carrier concentration measurements. The impact of Al doping on the ZnO thin films shows a very strong electrical signal, which manifested itself in the measured values of these parameters that are mentioned above. The results indicate the ability to tune various electrical parameters of the ZnO films through Al doping and growth temperature. Through response surface modeling, a sweet spot is identified where resistivity, mobility, and carrier concentration can be optimized to target values. While the mechanical characterization includes the piezoeffect characterization along with stress and strain analysis. This includes the comparison of different dielectrics films vis–vis ZnO films, followed by an assessment of 1D versus 2D piezoelectric structures including the wurtzite ZnO thin film. This includes the explanation of why these films have the highest piezoelectric coefficient in their class of materials and the role played by c-axis alignment in interpreting these observations. This establishes the criticality of assessing these quantities to come up with the right understanding and explanation for any observations seen in new class of thin films where the method of synthesis or doping is changed. Finally, the assessment of stress and strain in these film systems is presented with the role played by the substrate and the direction of the bending of the thin film. The experimental results include the design and fabrication of a “curved” stage that is used to induce the strains, and compute the associated stress generated, in quantifiable fashion to model the thin-film behavior.

Based on the results of Rizk and Saadat (The IoT Physical Layer, pp. 23–46, Springer, Berlin, 2018, [1], The IoT Physical Layer, pp. 47–68, Springer, Berlin, 2018, [2]), this chapter covers the use of Al-doped ZnO films as active channel material for TFT devices. It shows the need to have semiconducting behavior of the ZnO films and how this is modulated by the synthesis method, Al doping and synthesis temperature. Then, this chapter covers the process flow and goes over the unique challenges of fabricating on flexible substrate versus Si substrate and the associated mitigation techniques. These challenges include adhesion, film reliability, heat dissipation, and its low-temperature processing on flexible substrates. This is followed by the characterization of the TFT and its demonstration as best in its class, when it comes to this material system and associated fabrication constraints.

We propose a design of a compact photonic sensor based on two cascaded rings in a Vernier configuration integrated with a low-resolution flat-top planar echelle grating (PEG) de-multiplexer. The Vernier rings are composed of a filter and sensor rings. The sensor maps discrete changes in the index contrast, due to the presence of a target analyte, to a set of de-multiplexer channels. The channel number with highest transmittance is directly proportional to the incremental change of the effective index. Optical characteristics at different free spectral ranges (FSRs), ranging from 1 nm to 10 nm, have been studied. For example, if a filter ring FSR of 5 nm is selected, the corresponding sensor ring and de-multiplexer FSR are 4.7 and 5 nm, respectively, whereas the limit of detection (LOD) is \(620\times 10^{-6}\) RIU and \(1500\times 10^{-6}\) RIU for a ring round-trip loss of 0.1 and 0.72 dB, respectively. Meanwhile, higher sensitivity can be achieved for 1 nm FSR, where the corresponding LODs are \(160\times 10^{-6}\) RIU and \(300\times 10^{-6}\) RIU, respectively. Furthermore, by using a thermo-optic phase shift tuner, an ultra-low LOD down to \(80\times 10^{-6}\) RIU can be achieved.

In this chapter, we present the design challenges that are faced in a wireless sensor system to be placed in between the orthodontic braces and tooth. Such wireless systems are necessary, to indicate the bond failure between the braces and tooth, for the patient and the orthodontist as it saves both time and money. A humidity sensor-based implanted chip is selected for such purpose that will detect humidity leak once the bond breaks with power being supplied to it through inductive coupling with internal coil integrated in the chip and external coil placed in an external unit. It has shown how extensive study must be carried out in developing such a system especially with power transfer in such an environment factoring changing impedances due to mouth mechanics and movement dynamics. It also presents how data acquisition and transfer can take place in such a system. The chip has been designed using 180nm CMOS GLOBALFOUNDRIES process.

This chapter addresses the challenges and design strategies in body area network (BAN) transceivers. Stringent energy constraint in BAN application means the transceiver circuit must operate in energy-efficient manner. Yet the human body absorbing majority of radio frequency (RF) energy makes the RF-based transceivers unattractive for BAN applications. In this chapter, we discuss an alternative solution which utilizes the human body itself as a communication medium namely the body-coupled communication (BCC).

This chapter presents an ultra-low-power ECG processor for applications of IoT devices. It includes full system description consisting of ECG analog front end, ECG feature extraction and ventricular arrhythmia (VA) prediction system. Each of these components operate at ultra-low-power dissipation utilizing low-power circuits and architectures. The digital processing part is computation efficient that does ECG feature extraction using curve length transform (CLT) and discrete wavelet transform (DWT). Moreover, the VA predictor is implemented using linear classifier which is also hardware friendly.

This chapter discusses a scalable mixed-signal architecture for beamforming in time-delay arrays, where the time delays are realized by delaying the sampling clock of the receiver analog-to-digital converters. We derive the requirements on the timing correction and show how they are feasible in standard CMOS manufacturing processes. We then evaluate the impact of timing quantization of the array performance and compare the bit error rate (BER) performance of the proposed approach to phase arrays. For the same number of antennas, the BER of such an array is shown to be several orders of magnitudes lower than that of a phase array, especially at high fractional bandwidths. This chapter concludes by showing how a sub-picosecond requirement on time-delay generation for the beamformer is addressed using an antenna grouping strategy based on a hybrid architecture of a time and phase arrays. This architecture can relax the time correction requirements while enabling large arrays and fractional bandwidths with a modest BER penalty. Extensive simulations are used to evaluate the impact of antenna group sizes on the overall BER of the millimeter wave antenna system.

The Internet of Things (IoT) refers to a network type structure (like the Internet) that connects (unique) objects and things. Sensors and devices, integrated into all types of objects, are increasingly connected through wireless networks and, ultimately, the Internet. Already the existing ICT infrastructure accounts for roughly 10% of the global power consumption. By the year 2020, this network will contain 50 billion connected devices and the global IoT/machine-to-machine (M2M) communication market will have a volume of $ 0.5 trillion. Pervasive indoor wireless access has almost become a standard in the first world, but ensuring a thorough and economically sound wireless signal coverage throughout buildings is not a trivial problem. In-building Distributed Antenna Systems (I-DAS) extend wireless access from the base station to distributed antennas through a complex network of coaxial cables and power splitters. For high rise buildings and other multi-unit complexes, the initial cost of I-DAS (cabling and splitters) and the running costs of powering the network are quite significant, motivating the need to optimize the design of I-DAS networks. We propose to utilize Particle Swarm Optimization (PSO) to provide near-optimal network topology. Our PSO model uses Prüfer code representation to efficiently traverse through different spanning tree solutions. Our approach is scalable and robust, capable of producing I-DAS design advice for buildings beyond one hundred floors. We demonstrate that our model is capable of obtaining optimal solutions for small buildings and near-optimal solutions for tall buildings.

The most common operation of an IoT sensor is that of short activity bursts separated by long time intervals in sleep or listen modes. During the data bursts, sensed information has to be reliably communicated in real time without draining the energy resources of the sensor node. One way to save such resources is to efficiently code the data burst, use single-channel communication, and adopt ultra-low-power communication circuit techniques. Clock–data recovery (CDR) circuits are typically significant consumers of energy on traditional single-channel communication protocols. In this chapter, a novel single-channel protocol is presented that does not require any CDR circuitry. The protocol is based on the novel concept of a pulsed index where data are encoded to minimize the number of ON bits, move them to the LSB end of the packet, and transmit the ON bit indices in the form of a pulse stream. The pulse count is equal to the index of the ON bit. This protocol is called Pulsed-Index Communication (PIC). Beside the elimination of CDR, the implementation of PIC is very area-efficient, low-power, and highly tolerant of clocking differences between transmitter and receiver. Both an FPGA and an ASIC implementation of the protocol are presented and used to illustrate the performance, reliability, and power consumption features of PIC signaling. In particular, the chapter shows that for an ASIC implementation on 65 nm technology, PIC can reduce area by more than 80% and power by more than 70% in comparison with a CDR-based serial bit transfer protocol.

In this chapter, a novel algorithm for predicting ventricular arrhythmia (VA) is presented. It utilizes a unique set of ECG features with LDA classifier. These features are extracted from two consecutive heartbeats. The proposed method achieves a capability of predicting the arrhythmia up to 3 h before the onset with an accuracy of 99.1\(\%\) sensitivity of 98.95\(\%\) and precision of 98.39\(\%\).

MSERs (maximally stable extremal regions) belong to the most popular local image features with a wide range of highly practical applications, e.g., (to name a few) in image search and retrieval, object detection and recognition, image stitching, tracking mobile objects, etc. Low complexity of MSER detectors (combined with a regular structure suitable for hardware implementation) makes MSER an attractive option for IoT devices which may require vision capabilities to analyze and interpret their environments. In this chapter, we briefly discuss theoretical, algorithmic, and technical aspects of using MSER for such purposes. The presented results have contributed to the system-on-chip implementation of MSER detector which is also overviewed in this chapter. Additionally, we discuss prospective hardware implementations of even more efficient feature detectors based on MSERs.

This chapter presents an improved zero current switching (ZCS) control for high-gain inductor-based DC-DC converter targeting thermoelectric generator (TEG) for wearable electronics. The proposed ZCS control is an all-digital circuit that utilizes a simple finite state machine (FSM) and a 3-bit counter to locate the zero current point. In addition, an efficient push-pull circuit along with delay capacitance banks is used to tune the delay near the zero current point to reduce the estimated error. The proposed control circuit achieves 56 delay steps using 3 control bits while having a high resolution, which helps in maintaining the efficiency of the converter. The prototype chip is fabricated in 65 nm CMOS and occupies an area of less than 0.04 mm\(^{2}\). Measured results of the converter confirm 81\(\%\) peak efficiency at 55 \(\upmu \)W output power and 50 mV input voltage.

This chapter introduces an efficient reconfigurable, multiple voltage gain switched-capacitor DC–DC buck converter as part of a power management unit for wearable IoTs. The switched-capacitor converter has an input voltage of 0.6–1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1, 0.8 and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 \(\upmu \)A to 800 \(\upmu \)A. The switched-capacitor converter is designed and fabricated in 65 nm low-power CMOS technology and occupies an area of 0.493 mm\(^2\). The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80\(\%\) at a load current of 800 \(\upmu \)A and regulated load voltage of 1 V.

Thin-film, solid-state microbatteries represent a viable alternative for powering small form-factor IoT microsystems or storing the power harvested by energy microsensors. One major obstacle to their widespread use in integrated IoT systems has been the absence of a high-fidelity, physics-based, compact model describing their operation and enabling their design and verification in the same CAD environment as integrated power management systems. In this chapter, we develop and validate such models using a thorough analysis of the electrochemistry of a thin-film, solid-state, lithium-ion microbattery. One of our compact models is based on a behavioral linearization step where the nonlinear partial differential equations (PDEs) describing the microbattery electrochemistry are replaced with linear ones without virtually any loss in accuracy. We then apply the well-established methodology of Arnoldi-based model order reduction (MOR) techniques to develop a compact microbattery model capable of reproducing its input-output electrical behavior with less than 1% error with respect to the full nonlinear PDEs. The use of MOR results in more than 30X speedup in transient simulation.

This chapter presents a top-level design of the first self-powered SoC platform that can predict, with high accuracy, ventricular arrhythmia before it occurs. The system provides a very high level of integration in a single chip of mainstream modules that are typically needed to build biomedical devices. Hence, the platform could help in reducing the cost in designing not only for ECG monitoring systems, but for generic low-power health care devices. The platform consists of a graphene-based sensors to acquire ECG signals, an analog front-end to amplify and digitize the ECG, a custom processor to perform feature extraction and classification, a wireless transmitter to send the data to a point of care, and an energy harvesting unit to power the whole system. The platform consumes very low power that can be completely powered by the thermal energy generated from the human body. The system is imagined to be integrated within a necklace which can be worn by a patient comfortably. Hence, it can provide a continuous monitoring of the patient’s condition and connect him directly to his doctor for immediate attention if necessary.

This research presents a novel architecture of an ultra-low-power wearable system for congestive heart failure (CHF) monitoring using the continuous measurement of a patient’s weight to detect changes in body mass and fluid composition. Shoe-integrated sensor arrays are used to continuously measure the weight, and an electronic digital assistant, implemented in VLSI, is used to further analyze the acquired measurements in real time. To achieve ultra-low-power operation, the human body is used as a communication medium between the shoe-mounted sensors and the digital assistant. The single-channel behavior of the human body is accommodated with a novel, simple yet robust single-wire signaling technique that is called Pulsed-Index Communication (PIC). This signaling technique significantly reduces the system footprint and its overall power consumption as it entirely eliminates the need for circuitry dedicated to clock and data recovery. The proof-of-concept CHF system has been prototyped using a FPGA platform, the Virtex 7 from Xilinx. The prototype, which integrates models for footwear, body communication channel (BCC), and back-end digital electronics, has been rigorously and successfully tested. This highly modular system is being used to implement, analyze, and compare various pattern recognition algorithms for the early detection of congestive heart failure.

Ever-increasing design complexity and the skyrocketing cost of setting up a foundry have led to the globalization of the integrated circuit (IC) supply chain. A globalized and distributed IC supply fosters security threats such as reverse engineering, piracy, and hardware Trojans, and forces the stakeholders to revisit the trust at various steps in the IC design and fabrication flow. Among the ensemble of solutions proposed to address hardware-related trust issues, logic locking has gained significant interest from the research community. A series of defense techniques and attacks have been developed over the past few years. This chapter presents a comprehensive survey of recent research efforts in the field of logic locking. The emphasis is on the subtle difference between the logic locking attacks/countermeasures in terms of the threat models employed and strengths/vulnerabilities of existing logic locking techniques.