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Journal of Electronic Testing
Published in: Journal of Electronic Testing 4/2018

06-06-2018

Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition

Authors: Ying Zhang, Li Ling, Jianhui Jiang, Jie Xiao

Published in: Journal of Electronic Testing | Issue 4/2018

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Abstract

With increasing power density in modern integrated circuits, thermal issues are becoming a critical problem in System-on-a-Chip (SoC) testing. In this paper, we develop the thermal-aware test scheduling methods using Voltage/Frequency Scaling (VFS) and Test Partition (TP) to reduce the expensive Test Application Time (TAT). First, we develop a quick temperature estimation method in test scheduling to ensure the test temperature within the given range. Second, we propose a thermal-aware test scheduling method based on the mixed-integer linear programming model (MILP) (called STP-M) that applies VFS and TP to search the optimum scheduling and further reduce the TAT. Third, we develop a heuristic method based on Rectangular Strip Packing (called H-RSP) to quickly access the quasi-optimal scheduling. The experimental results on ITC’02 benchmarks showed that the STP-M obtains the most optimized result for every benchmark and saved 15.5% and 8.0% TAT on average compared with the existing works, while H-RSP takes less than 10 seconds to access the quasi-optimal scheduling that is close to that of STP-M.
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Metadata
Title
Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition
Authors
Ying Zhang
Li Ling
Jianhui Jiang
Jie Xiao
Publication date
06-06-2018
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 4/2018
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-018-5733-x

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