Towards a framework for dealing with system timing in Very High Level Silicon Compilers

The design of a VLSI system typically involves many decisions relating to several levels of timing detail. Examples include choices relating to timing disciplines, architectural and circuit design paradigms, the number of clock phases, the number of amplification stages, the sizes of specific transistors, and the temporal behavior demanded of specific input signals (such as stability criteria they must obey). This paper discusses a framework for dealing with system timing issues in the context of very high level silicon compilers intended to aid in mapping abstract behavioral specifications into VLSI circuits. The paradigm considered allows the details of system timing to be gradually introduced as a design progresses. During the early stages of a design, no timing details need be explicit, and the only temporal constraints arise due to functionality, causality and stability criteria. As a design evolves, and decisions relating to resource allocation, computation schedules, timing and clocking disciplines are made, the temporal constraints on signals evolve correspondingly. If the external environment in which a system resides imposes any a priori temporal constraints, such constraints can be explicitly included in the initial specification, and accounted for in the synthesis process. The framework supports synchronous and asynchronous (self-timed) disciplines, multiphase-clocks, as well as techniques that bear on optimizations of performance metrics such as power and area.