Using Artificial Neural Networks for Analog Integrated Circuit Design Automation

Despite the efforts in recent years, the lack of automation in analog integrated circuit (IC) design creates a large design productivity gap. The level of automation provided by electronic design automation (EDA) tools for analog IC design is not even close to the level of automation found in digital design. Moreover, as analog IC design follows very heterogeneously and knowledge-intensive approaches, its automation is still an open research field. In this chapter, we introduce the analog IC design problem and explore how the advances in machine learning (ML) can pave the way for new EDA tools.

In this chapter, recent works on analog integrated circuit (IC) sizing and layout automation are explored. It first starts with an overview of existing works where machine learning (ML) techniques are applied to analog ICs sizing. Then, the three major methodologies used in the automatic layout of analog integrated circuits are presented. These serve to contextualize the placement process and help to identify how data can be considered for its automation.

This chapter starts with a review of modern machine learning (ML) techniques. Advantages and disadvantages of several ML methods taking into account its application to the automation of analog integrated circuit sizing and placement are considered, in order to create a clear picture of why artificial neural networks (ANNs) are a good fit for both these tasks. Then, an overview of ANNs is presented to introduce the key concepts that are needed for the implementation of the models described in Chaps. 4 and 5. A brief overview of how the ANNs learning mechanism works, the optimization techniques to speed up the convergence of the learning algorithm, and the regularization techniques used to help the models to generalize better to data that they have not seen during training is presented describing the models’ hyper-parameters that must be tuned.

In this chapter, two artificial neural network (ANN) models are proposed for analog integrated circuit (IC) sizing. The first one, a regression-only model, serves as a proof of concept; i.e., the applicability of ANNs to analog IC sizing is tested. In this architecture, we explore how an ANN that is trained using circuit sizing solutions from previous optimizations can learn the design patterns of the circuit (a single circuit topology for differential amplifiers is considered in each training phase). The second one, a classification and regression model, is also presented. This architecture selects not only the most appropriate circuit topology, but also its respective sizing given the target specification (more than one topology is considered in the training phase).

Layout generation is the task of the analog integrated circuit (IC) design flow that both lays the devices (i.e., placement), whose dimensions were previously determined for the selected topology, out in the chip and connects them (i.e., routing), creating the masks for future manufacturing. In this chapter, exploratory research using artificial neural networks (ANNs) is conducted to automate the placement task of analog IC layout design. The proposed methodology abstracts the need to explicitly deal with topological constraints by learning reusable design patterns from validated legacy layout designs. The ANNs are trained on a dataset of an analog amplifier containing thousands of placement solutions for 12 different and conflicting layout styles/guidelines and used to output different placement alternatives, for sizing solutions outside the training set, at push-button speed. Ultimately, the methodology can offer the opportunity to reuse all the existent legacy layout information, either generated by layout designers or electronic design automation (EDA) tools. In the first section of this chapter, the novel ideas proposed by this methodology are outlined. Additional detail on the circuit used to demonstrate the methodology, how the dataset is structured, the general architecture of the proposed ANN, and metrics used to evaluate the models is provided in Sect. 5.2. Afterward, in Sect. 5.3, the tests conducted to assess the viability of using an ANN to automatically generate analog IC layout placements are fully detailed. In Sect. 5.4, the conclusions taken from the developments described in this chapter and future research directions are outlined.