Wireless Cortical Implantable Systems

The early roots of electrophysiology can be traced back to the Italian scientist Galvani (1737–1798) who discovered that the living tissue of frog muscles exhibits electrical potential. Electrical observation studies on living animal subjects were continued for a century. Hans Berger (1873–1941) succeeded to record the first human electroencephalogram (EEG) signal in 1924, using a Siemens double-coil galvanometer [1]. Shortly thereafter, several neurological institutes equipped with vacuum tube recording systems were established worldwide. Continuous improvements in the field not only supported research in the life science domain, but also enabled the clinical treatment of some diseases.

Chronic monitoring of action potentials associated with the electrical activity of the motor cortex in an enriched environment is an emerging health care technology. Feature extraction of the action potentials recorded from a large number of neurons enables the successful functional mapping of the motor cortex which can be used to develop an autonomous system replacing some cognitive functions of the brain [1]. However, extensive recording in vivo requires full compliance with strict safety requirements.

Issues related to the voltage regulation in remotely powered implants are discussed in this chapter. Two on-chip low drop out (LDO) voltage regulators are presented which target two different specification sets, and which are incorporated into two versions of the Neuro+ IC. The first LDO voltage regulator is proposed to support the Neuro+I and provides 1.8 V output voltage. The regulator is stable over the full range of alternating load current and provides fast load regulation, which is achieved by applying a time -domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024 %, and a PSRR of 37 dB at a 1 MHz power carrier frequency . The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6 \(\upmu \)s, at full load transition. The total ground current including the bandgap reference circuit is \(28\,\upmu \)A and the active chip area measures 0.104 mm\(^{2}\) in a \(0.18\,\upmu \)m CMOS technology. The second LDO voltage regulator targets the Neuro+II and generates a 1.2 V output voltage. The regulator is stable over the full range of the load current up to 20 mA and supports burst mode of operation using a robust start-up circuit in the bandgap reference circuit. The Regulator achieves a line and load regulation of 3.45 % and 0.11 V/A, respectively. The sample prototype occupies a silicon area of 0.073 mm\(^{2}\) in a \(0.18\,\upmu \)m CMOS technology.

This chapter presents a neural recording amplifier array suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology which utilize a CMOS differential pair input stage. The proposed architecture , which is referred to as partial OTA sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to a very low NEF. The effect of mismatch on crosstalk between channels and the trade-off between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a \(-3\) dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at \(3.5\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\) and the power consumption is \(7.92\,\upmu \mathrm{{W}}\) from a 1.8 V supply, which corresponds to \(\mathrm{NEF}=3.35\). The worst-case crosstalk and CMRR within the desired bandwidth are \(-43.5\) dB and 70.1 dB, respectively, and the active silicon area of each amplifier is \(256\,\upmu \mathrm{{m}}\times 256\,\upmu \mathrm{{m}}\) in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology.

This chapter presents three different circuits and systems architectures enabling multichannel neural recording. These systems preserve the temporal information of the recording sites by avoiding time -multiplexed operation of the ADC. Moreover, various system-level original concepts are introduced that improve trade-offs between noise, power, and silicon area. Oversampling is introduced in Sect. 5.2 as a useful technique to improve the noise efficiency factor (NEF) at system level. Since the total power consumption is dominated by low-noise front-end amplifiers, any increase in the power consumption of the ADC due to the oversampling, has a negligible impact on the overall power consumption of the system. Nevertheless, the input-referred noise is reduced using an oversampling ADC, as the integrated noise bandwidth is reduced by increasing the oversampling ratio, which results in an improved noise efficiency factor (NEF). A 16-channel neural action potential recording IC is presented as a proof-of-concept prototype. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain -stages utilizing a novel common-mode feedback (CMFB) circuit. An oversampling delta modulator (DM) serves as an ADC in order to improve the NEF of the recording system. Moreover, in-site compression is achieved by converting the temporal difference of the input neural signal. The DM employs a novel dynamic voltage comparator with a partial reset preamplifier, which enhances the mean time to failure of the modulator. The proposed architecture is fabricated in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology. The 16-channel system consumes \(220\,\upmu \mathrm{{W}}\) from a 1.2 V power supply. The SNDR is measured at 28.3 and 35.9 dB at the modulator and demodulator outputs, respectively. The total integrated in-band input-referred noise is measured at \(2.8\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\), which corresponds to \(\mathrm{{NEF}}=4.6\) for the entire system. Section 5.3 introduces the application of algebraic coding to a multi-channel neural recording system. Walsh-Hadamard coding enables back-end hardware sharing between recording channels employing a single ADC, thereby avoiding time -multiplexing. A single ADC converts the analog superposition of multiple channels. Thus, the dynamic range of the ADC is effectively shared between channels benefiting from the sparsity characteristics of the channels in space domain . Also, noise coupling, interference, and crosstalk are reduced, thanks to the low-impedance and low-swing wired summation of the channels in the analog domain . A 16-channel recording system is developed as a test vehicle. This system provides 60 dB of accurate gain for signal amplification and is programmable by steps of 19 dB. A single 10-bit SAR ADC is used for data conversion. The system is implemented in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology and occupies a silicon area of \(1.99\,\mathrm{{mm}}^{2}\). Placing the ADC outside of the sensor plane enables reducing the channel’s pitch, with respect to the standard value of \(400\,\upmu {\mathrm{{m}}}\) which is used in Utah’s MEA. The input-referred noise of a single channel integrated from 100 Hz to 100 kHz is simulated at \(4.1\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\) while consuming \(359\,\upmu \mathrm{{W}}\) from a 1.2 V power supply, which results in a system-level NEF of 5.6. Finally, a 64-channel neural recording system-on-a-chip (SoC) is presented in Sect. 5.4. The system is composed of an on-chip half-wave voltage rectifier, low-voltage bandgap reference circuit, LDO voltage regulator, on-chip reference generator, 64-channel mixed-signal core with dedicated 8-bit SAR ADC per channel, and an on-chip digital ASIC for packet generation , scrambling, and synchronization. A programmable power management technique is proposed which enables dynamic power scaling (DPS) of the mixed-signal core. Applying the DPS technique, the power consumption of each individual channel is reduced by 20.4 % which is equivalent to a reduction of 16 % in the total power consumption of the analog/mixed-mode front-end. The total power dissipation of the SoC is measured at 3.26 mW from a 1.2 V power supply. The SoC is fabricated in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology and occupies an active silicon area of \(17.5\,\mathrm{{mm}}^{2}\).

A CMOS impulse radio ultra wide-band (IR-UWB) digital transmitter is presented as the up-link communication module of a 64-channel parallel cortical recording implanted system. The transmitter is capable of transmitting live recording data at programmable rates of 1.5/3/6/12 Mb/s using a single 4 MHz clock. A novel all-digital delay locked loop (AD-DLL) serves as an 8-array pulse position modulator (PPM) enabling aggressive duty-cycling of the transmitter (Tx). The 8-PPM modulation scheme provides intrinsic scrambling of the pulse position which attenuates the spectral peaks. The UWB pulse generator is implemented using finite impulse response synthesis of the raised-cosine pulse. A symmetric pulse-combining technique is proposed to reduce the number of power amplifier elements by half, which enables reducing the parasitic at the Tx output, as well as enhancing the tuning range capability of the transmitter. The transmitter is implemented in a 90 nm CMOS technology, consumes 540 \(\upmu \)W from a 1 V power supply, which results in an energy efficiency of 45 pJ/bit with an output power of \({-}26\) dBm. The active silicon area is \(0.37\,\mathrm{{mm}}^{2}\). The modulated spectrum of the transmitter is fully compliant with USA Federal Communications Commission (FCC) effective isotropic radiated power (EIRP) modulation masks for indoor and outdoor UWB communication devices.

In this book, low-power circuits and systems techniques for data acquisition and transmission in wireless cortical implants are presented. Action potentials are considered the target group of neural signals associated with motor cortex activities. The proposed neural recording system which is named Neuro+II is composed of a power conversion chain, an analog/mixed-mode signal conditioning circuit, a digital baseband signal processing unit, and an IR-UWB transmitter.