Graphene Nanoelectronics

CMOS transistors have been scaling exponentially in the past two decades and the intrinsic device performance has followed a commensurate scaling trend. Prior to the 90-nm node, mere shrinking of the device dimensions, following Dennard’s scaling theory, was sufficient to guarantee increased device performance; beyond the 90-nm node, new innovations were necessary to continue the historical performance scaling trend. Strain engineering and high-k/metal gate technologies were the two major innovations that made the commensurate performance scaling in the past decade possible. However, it appears that new device structures and performance boosters will continue to be the need of the future. This chapter provides a basic overview of MOSFET scaling trend, followed by a discussion of MOSFET operation in deca-nanometer scale based on the so-called virtual source injection model. A simple analytical model for transistor I–V characteristics and intrinsic transistor delay is provided and used to quantify the historical trends of MOSFET performance scaling. Carrier velocity is shown to be the main driver for the continued MOSFET performance increase. Finally, the prospect of velocity increase is reviewed for strained Si, Ge, and compound semiconductors.

This chapter provides an experimental overview of the electrical transport properties of graphene and graphene nanoribbons, focusing on phenomena related to electronics applications. Section 2.1 gives a brief description of the band structure. Section 2.2 discusses the effect of various scattering mechanisms in 2D sheets and nanoribbons and compares the characteristics of exfoliated and synthesized graphene. The physics of high-bias transport in graphene field effect transistors is described in Sect. 2.3. Section 2.4 gives a brief summary and outlook.

This chapter begins with an overview of digital and analog semiconductor technology. Following this, tradeoffs between various device designs are discussed for Si FETs. Analog (RF) applications require a low access resistance and small mobility degradation from dielectrics—the former is discussed in detail in this chapter, while the latter is the topic of Chap. 9. Digital FETs need certain criteria to be met—foremost amongst them being bandgap opening and complementary operation. Both these topics are discussed in detail in this chapter. Geometrical scaling of graphene FETs—including width and length scaling—is discussed along with implications for edge-scattering and methods to reduce it. Circuit implementations of graphene FETs are looked into including mixers, frequency multipliers, and inverters. A few non-FET structures are also looked at such as the Klein tunneling transistor.

This chapter provides an outlook of some important state variables used to enable graphene based nanoelectronic devices. State variables are physical representations of information used to perform information processing via memory, logic and transmission functionality. Recent advances in scalable graphene and controllable nanoribbons has provided hope for graphene based nanodevices, including more exotic devices that employ alternative state variables. This chapter will discuss a few such devices including electron charge as used in FET devices, electron spin as used in Spin FET devices, pseudospin as used in BiSFET devices, phonons as used in thermal logic and molecular charge as used in atomic mechanical switches.

In this chapter, a framework is developed for comparison of different post-CMOS interconnect technologies using physical models of transport mechanisms for these novel interconnects. In the first part of the chapter, an overview of CMOS interconnects is provided with an emphasis on the impact of scaling on the performance and energy dissipation of local (<100 gate pitches) interconnects. The second part of the chapter deals with the delay modeling of novel interconnects. The upper bound on the performance of novel interconnects is benchmarked against their conventional CMOS counterparts. A set of guidelines is derived at the device and circuit level for post-CMOS technologies.

This chapter starts off with a discussion on the history of graphite growth on SiC. It then gives an overview of various methods to grow epitaxial graphene on SiC; methods discussed include growth on various polytypes, at different vacuum levels and gas flows, and on both the Si- and C-face of SiC. Structural and electronic properties of these films are looked into along with carrier mobility results from Hall-bar and FET-structures where available.

In this chapter, the production of graphene by chemical vapor deposition (CVD) is discussed. CVD is widely used in the microelectronics industry in processes involving the deposition of thin films of various materials. The deposition is made from precursors in the gas phase which adsorb on the target surface producing a condensed phase of a specific material. The attractiveness of the generation of graphene by CVD is based on the fact that this technique allows for scalability as well as low cost.

The “physical” separation of graphite layers with adhesive tape was a novel approach that spawned a flurry of activity but the chemical separation of graphite layers has been known for decades. The chapter starts off with a historical perspective of chemical exfoliation. The following topics are then discussed in detail: the morphology of chemically converted graphene (CCG) and graphene oxide (GO); models and supporting experiments that provide insight into the structural properties of GO; electrical characterization of CCG and GO; improvements made in CCG formation and functionalization of CCG; and, obtaining graphene ribbons from carbon nanotubes.

Graphene, a monolayer of sp² bonded carbon atoms, has recently attracted wide-spread attention because of its unique transport and physical properties that are appealing for a wide range of electronic applications. Integration with scalable high-κ dielectrics is important for the realization of graphene-based top-gated electronic devices including field effect transistors (FETs) and new logic device concepts. These gate dielectrics are expected to be thin (2–30 nm), with minimal trapped and mobile charges that otherwise would negatively affect device performance. In addition, the dielectrics are expected to enable operation at very high frequencies (including the THz range) needed for next generation radiofrequency applications, improve the channel mobility by screening charged impurities, and reduce the high leakage currents observed in traditional silicon dioxide (SiO₂) gated devices.