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Journal of Electronic Testing
Published in: Journal of Electronic Testing 2/2019

02-05-2019

A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip

Authors: Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya

Published in: Journal of Electronic Testing | Issue 2/2019

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Abstract

Networks-on-chip (NoC) provide the communication infrastructure for high-speed and large-scale computation that integrates several IP-cores on a single die. Faults on network channels severely degrade system performance and throughput. This paper presents a distributed and online mechanism for detecting and locating stuck-at faults (SAFs) in NoC channels. We also study the effects of such faults on various network performance metrics. The inherent parallelism present in the architecture is utilized to design a scheduling scheme that reduces the overall test time and overhead significantly. The proposed test solution scales well with network size, channel width, and network topology. Hardware synthesis based on FPGA shows that it needs small area overhead and low test time compared to prior approaches. Furthermore, it improves packet latency and reduces energy consumption.
previous article A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs
next article Characterization Method for Integrated Magnetic Devices at Lower Frequencies (up to 110 MHz)

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Footnotes
1
In a test iteration either the nodes on an odd/even diagonal level execute the 1-step algorithm only. This node selection is comparable to a coin tossing that results in either head/tail mark where appearance of head results in selection of nodes at an odd diagonal level. On the contrary, nodes on an even diagonal level may be selected on the appearance of tail. The diagonal model (D-Model) and Toss-Model are interchangeable used in the rest of the paper.
 
2
The labels R1, R2 in this figure and later part of the paper represent TR=I, TR=II, respectively.
 
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Metadata
Title
A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip
Authors
Biswajit Bhowmik
Santosh Biswas
Jatindra Kumar Deka
Bhargab B. Bhattacharya
Publication date
02-05-2019
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 2/2019
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-019-05792-1

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