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01-07-2010 | Technical Paper | Issue 7/2010

Microsystem Technologies 7/2010

A novel CMOS process compatible high performance parallel-stacked RF spiral inductor

Journal:
Microsystem Technologies > Issue 7/2010
Authors:
D. K. Jair, Ming Chun Hsieh, C. S. Lin

Abstract

In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications.

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