Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Journal of Electronic Testing
Published in: Journal of Electronic Testing 1/2019

02-02-2019

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

Authors: Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell

Published in: Journal of Electronic Testing | Issue 1/2019

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

This paper deals with the analysis of the impact of process variations on the detection of resistive short defects, in the context of a logic-based test. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). For both defect types, simple analytical models are proposed that permit to evaluate the robust detectability range in presence of process variations. These models rely on a pre-characterization of the gate library through Monte-Carlo simulation and permit to evaluate the detectability range of a given defect without performing any fault simulation. These models are applied to perform a comparative analysis of 28 nm Bulk and FDSOI (Fully Depleted Silicon-On-Insulator) technologies, considering both regular-VT and low-VT devices. The influence of operating conditions on defect detectability range is also investigated.
previous article An Optimized NS2 Module for UHF Passive RFID Systems
next article Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
Show more products
Literature
1.
Nowak EJ et al (2004) Turning silicon on its edge double gate CMOS/FinFET technology. IEEE Circuits and Devices Magazine 20(1):20–31MathSciNetCrossRef
2.
Iwai H (2008) CMOS technology after reaching the scale limit Proc 8th International Workshop on Junction Technology (IWJT), pp1–2
3.
Magarshack P et al (2013) UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency Proc Design Automation & Test in Europe (DATE), 952–957
4.
Mäkipää J et al (2013) FDSOI versus BULK CMOS at 28nm node which technology for ultra-low power design?, Proc IEEE Int’l Symp on Circuits and Systems (ISCAS), pp. 554–557
5.
Makovejev S et al (2015) Self-heating in 28 nm bulk and FDSOI," EUROSOI-ULIS: proc. joint international EUROSOI workshop and Int’l conference on ultimate integration on Silicon, pp. 41–44
6.
Renovell M, Hue P, Bertrand Y (1995) The concept of resistance interval: a new parametric model for realistic resistive bridging fault. Proc VLSI Test Symp (VTS), pp184–189
7.
Polian, I. et al (2005) Resistive bridge fault model evolution from conventional to ultra-deep submicron. Proc. IEEE VLSI Test Symposium (VTS), pp. 343–348, 2005
8.
Rossello JL, de Benito C, Bota SA, Segura J, (2007)Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. Proc Design, Automation & Test in Europe (DATE), p. 6
9.
Engelke P et al (2004) The pros and cons of very-low-voltage testing: an analysis based on resistive bridging faults. Proc VLSI Test Symp (VTS), pp. 171–178
10.
Engelke P et al (2008) On detection of resistive bridging defects by low-temperature and low-voltage testing. IEEE Trans on Computer-Aided Design, vol. 27, no. 2, pp. 327–338
11.
Villacorta H, Champac V, Bota S, Segura J (2012) Resistive bridging defect detection enhancement under parameter variations combining low VDD and body bias in a delay based test. Microelectron Reliab 52(11):2799–2804
12.
Ingelsson, B. et al., "Process variation-aware test for resistive bridges," in IEEE Trans Computer-Aided Design, vol. 28, no. 8, pp. 1269–1274, 2009
13.
Zhong S et al (2013) Impact of PVT variation on delay test of resistive open and resistive bridge defects Proc Int’l Symp on Defect and Fault Tolerance (DFTS), pp. 230–235
14.
Karel A et al (2016) Comparative study of bulk, FDSOI and FinFET technologies in presence of a resistive short defect. Proc Latin-American Test Symp (LATS), pp. 129–134
15.
Karel A et al (2016) Impact of VT and body- biasing on resistive short detection in 28nm UTBB FDSOI - LVT and RVT configuration. Proc IEEE CS Annual Symp on VLSI (ISVLSI), pp. 164–169
16.
Karel A et al (2018) Impact of process variations on the detectability of resistive short defects: comparative analysis between 28nm bulk and FDSOI technologies. Proc Latin-American Test Symp (LATS), p5
17.
Skotnicki T et al (2008) Innovative materials, devices, and CMOS Technologies for low-Power Mobile Multimedia. IEEE Trans Electron Devices 55(1):96–130CrossRef
18.
Takayasu S et al (2006) Fully-depleted SOI CMOS circuits and technology for ultra-low power application. Springer,
19.
Pelloux-Prayer B et al (2013) Performance analysis of multi-VT design solutions in 28nm FD-SOI technology. Proc. SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1–2
20.
Karel A et al (2017) Influence of body- biasing, supply voltage and temperature on the detection of resistive short defects in FDSOI technology. IEEE Trans Nanotechnol 16(3):417–430CrossRef
21.
Stuart A, Ord K (2010) Kendall's Advanced Theory of Statistics, vol 1, 6th edn. John Wiley & Sons, New YorkMATH
Metadata
Title
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies
Authors
Amit Karel
Florence Azaïs
Mariane Comte
Jean-Marc Gallière
Michel Renovell
Publication date
02-02-2019
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 1/2019
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-019-05776-1

Other articles of this Issue 1/2019

Journal of Electronic Testing 1/2019 Go to the issue

OriginalPaper

A Layout-Based Rad-Hard DICE Flip-Flop Design

OriginalPaper

Metric-Driven Verification Methodology with Regression Management

EditorialNotes

Editorial

OriginalPaper

An Optimized NS2 Module for UHF Passive RFID Systems

Announcement

New Editors – 2019

OriginalPaper

RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems