2007 | OriginalPaper | Chapter
Asymmetrical Triple-Gate FET
Authors : Meng-Hsueh Chiang, Jeng-Nan Lin, Keunwoo Kim, Ching-Te Chuang
Published in: Simulation of Semiconductor Processes and Devices 2007
Publisher: Springer Vienna
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A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n
+
p
+
) polysilicon gates. CMOS-compatible V
T
’s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.