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02-12-2019 | Technical Paper

Characterization of single-ended 9T SRAM cell

Authors: Chandramauleshwar Roy, Aminul Islam

Published in: Microsystem Technologies | Issue 5/2020

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Abstract

We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect.

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Alioto M, Palumbo G, Pennisi M (2010) Understanding the effect of process variations on the delay static and domino logic. IEEE Trans VLSI Syst 18(5):697–710CrossRef

Aly RE, Bayoumi MA (2007) Low-power cache design using 7T SRAM cell. IEEE Trans Circuits Syst II Exp Briefs 54(4):318–322CrossRef

Amlani I, Lewis J, Lee K, Zhang R, Deng J, Wong HSP (2006) First demonstration of AC gain from a single-walled carbon nanotube common-source amplifier. In: Proc. int. electron devices meet., 2006, pp 1–4

Azizi N (2003) Low-leakage asymmetric-cell SRAM. IEEE Trans VLSI Syst 11(4):701–715CrossRef

Carlson AE (2018) Device and circuit techniques for reducing variation in nanoscale SRAM. Ph.D. dissertation, Univ. California Berkeley, Berkeley, CA

Chang MH, Chiu YT, Lai SL, Hwang W (2011) A 1 kb 9T subthreshold SRAM with bit-interleaving scheme in 65 nm CMOS. In: Proc. int. symp. low power electronics and design (ISLPED), Aug. 1–3, 2011, pp 291–296

Chang MH, Chiu YT, Hwang W (2012) Design and iso-area vmin analysis of 9t subthreshold sram with bit-interleaving scheme in 65-nm CMOS. IEEE Trans Circ Syst II Exp Briefs 59(7):429–433

Deng J, Wong HSP (2007a) A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part I: model of the intrinsic channel region”. IEEE Trans Electron Dev 54(12):3186–3194CrossRef

Deng J, Wong HSP (2007b) A compact SPICE model for carbon-nanotube field effect transistors including nonidealities and application-part II: full device model and circuit benchmarking. IEEE Trans Electron Dev 54(12):3195–3205CrossRef

Guo Z, Carlson A, Pang LT, Doung KT, Liu TJK, Nikolic B (2009) Large-scale SRAM variability characterization in 45 nm CMOS. IEEE J Solid State Circ 44(11):3174–3192CrossRef

Hattori S, Sakurai T (2004) 90% write power saving SRAM using sense amplifying memory cell. IEEE J Solid State Circ 39(6):927–933CrossRef

Hennessy J, Patterson D (2003) Computer architecture: a quantitative approach, 3rd edn. Morgan Kaufmann, New YorkMATH

Islam A, Hasan M (2012a) Leakage characterization of 10T SRAM cell. IEEE Trans lectron Dev 59(3):631–638CrossRef

Islam A, Hasan M (2012b) A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM cell. Microelectron Reliab 52(2):405–411CrossRef

Islam A, Hasan M, Arslan T (2012) Variation resilient subthreshold SRAM cell design technique. Int J Electron 99(9):1223–1227CrossRef

Kang SJ, Kocabas C, Ozel T et al (2007) High performance electronics using dense perfectly aligned arrays of single walled carbon nanotube. Nat Nanotechnol 2:230–236CrossRef

Karandikar A, Parhi KK (1998) Low power SRAM design using hierarchical divided bit-line approach. In: Proc. Int. Conf. Comput. Des., pp 82–88

Kulkarni JP, Kim K, Roy K (2007) A 160 mV robust schmitt trigger based subthreshold SRAM. IEEE J Solid State Circ 42(10):2303–2313CrossRef

Liu Z, Kursun V (2008) Characterizatuon of a novel nine-transistor SRAM cell. IEEE Trans VLSI Syst 16(4):488–492CrossRef

Lu CY, Chuang CT (2013) A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance. In: IEEE 26th international SOC conference (SOCC), Erlangen, 4–6 Sep 2013, pp 325–329

Lu CY et al (2012) A 0.33 V, 500 KHz, 3.941JW 40 nm 72 Kb 9T subthreshold SRAM with ripple bit-line structure and negative bit-line write-assist. IEEE Trans Circ Syst II Exp Briefs 59(12):863–867

Mai KW (1998) Low-power SRAM design using half-swing pulse-mode techniques. IEEE J Solid State Circ 33(11):659–1671CrossRef

Mintmire JW, White CT (1998) Universal density of states for carbon nanotubes. Phys Rev Lett 81(12):2506–2509CrossRef

Mizuno H, Nagano T (1996) Driving source-line cell architecture for sub-1-V high-speed low-power applications. IEEE J Solid State Circ 31(4):552–557CrossRef

Nalam S, Calhoun BH (2009) Asymmetric sizing in a 45 nm 5T SRAM to improve read stability over 6T. In: Proc. IEEE 2009 custom integrated circuits conference (CICC), 2009, pp 709–712

Nanoscale Integration and Modeling (NIMO) Group (2019) Arizona State University (ASU). [Online]. http://ptm.asu.edu/

Noguchi H, Okumura S, Iguchi Y, Fujiwara H, Morita Y, Nii K, Kawaguchi H, Yoshimoto M (2008) Which is the best dual-port SRAM in 45-nm process technology?—8T, 10T single end, and 10T differential. In: Proc. IEEE ICICDT, Jun. 2008, pp 55–58

Patil N, Deng J, Lin A, Wong HSP, Mitra S (2008) Designed methods for misaligned and mispositined carbon nanotube immune circuits. IEEE Trans Comput Aid Des Integr Syst 27(10):1725–1736CrossRef

Pelgrom M, Duinmaijer A, Welbers A (1989) Matching properties of MOS transistors. IEEE J Solid State Circ 24(5):1433–1440CrossRef

Rabaey JM, Chandrakasan A, Nikolic B (2005) Digital integrated circuits: a design perspective, 2nd edn. Prentice-Hall of India, New Delhi

Sachid AB, Hu C (2012) Denser and more stable SRAM using FinFETs with multiple fin heights. IEEE Trans Electron Dev 59(8):2037–2041CrossRef

Seevinck E, List F, Lohstroh J (1987) Static-noise margin analysis of MOS SRAM cells. IEEE J Solid State Circ SC-22:748–754CrossRef

Semiconductor Industry Association (SIA) (2011) International Technology Roadmap for Semiconductors 2011 Edition. http://www.itrs.net/reports.html

Semiconductor Industry Association (SIA) (2013) International technology roadmap for semiconductors 2013 edition. http://www.itrs.net/reports.html

Singh J et al (2008) A single ended 6T SRAM cell design for ultra-low-voltage applications. IEICE Electron Express 5(18):750–755CrossRef

Stanford University (2019) CNFET model website, 2019. http://nano.stanford.edu/models.php

Sven L et al (2013) A 65 nm 32 b subthreshold processor with 9T multi-Vt SRAM and adaptive supply voltage control. IEEE J Solid State Circ 48(1):8–19CrossRef

Teman A et al (2011) A 250 mV 8 kb 40 nm ultra-low power 9T Supply Feedback SRAM (SF-SRAM). IEEE J Solid State Circ 46(11):2713–2726CrossRef

Tschanz JW, Kao JT, Narendra SG, Nair R, Antoniadis DA, Chandrakasan AP, De V (2002) Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE J Solid State Circ 37(11):1396–1402CrossRef

Tu MH et al (2012) A single-ended disturb-free 9T Subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing. IEEE J Solid State Circ 47(6):1469–1482CrossRef

Vaddi R, Dasgupta S, Agarwal RP (2010) Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS. IEEE Trans Electron Dev 57(3):654–664CrossRef

Varma N, Kong J, Chandrakasan AP (2008) Nanometer MOSFET variation in minimum energy subthreshold circuits. IEEE Trans Electron Dev 55(1):163–174CrossRef

Wang B et al (2014) Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement. In: IEEE Trnas. circuits syst. I, reg. papers, 2014. https://doi.org/10.1109/tcsi.2014

Yang B, Kim L (2005) A low-power SRAM using hierarchical bit line and local sense amplifiers. IEEE J Solid State Circ 40(6):1366–1376CrossRef

Yoshimoto M (1983) A 64 kb CMOS RAM with divided word line structure. In: Tech. Dig. IEEE int. solid-state circuits conf., pp 58–59

Title: Characterization of single-ended 9T SRAM cell
Authors: Chandramauleshwar Roy
Aminul Islam
Publication date: 02-12-2019
Publisher: Springer Berlin Heidelberg
Published in: Microsystem Technologies / Issue 5/2020
Print ISSN: 0946-7076
Electronic ISSN: 1432-1858
DOI: https://doi.org/10.1007/s00542-019-04700-z

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