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1990 | OriginalPaper | Chapter

Compiling for the Hybrid Architecture

Author : Robert A. Iannucci

Published in: Parallel Machines: Parallel Machine Languages

Publisher: Springer US

Included in: Professional Book Archive

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This chapter considers the task of transforming dataflow program graphs into partitioned graphs, and thence into PML. Section 4.1 extends the work of Section 1.1 by completing the description of DFPG’s. Section 4.2 discusses the issues involved in generating partitioned code from DFPG’s. Section 4.3 presents the design of a suitable code generator.

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Metadata
Title
Compiling for the Hybrid Architecture
Author
Robert A. Iannucci
Copyright Year
1990
Publisher
Springer US
Book
Parallel Machines: Parallel Machine Languages

Print ISBN: 978-1-4612-8827-5

Electronic ISBN: 978-1-4613-1543-8

Copyright Year: 1990

DOI
https://doi.org/10.1007/978-1-4613-1543-8_4