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The Journal of Supercomputing
Published in: The Journal of Supercomputing 8/2015

01-08-2015

Design and analysis of a mesh-based wireless network-on-chip

Authors: Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh

Published in: The Journal of Supercomputing | Issue 8/2015

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Abstract

Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long-distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock-free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture.
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Metadata
Title
Design and analysis of a mesh-based wireless network-on-chip
Authors
Wen-Hsiang Hu
Chifeng Wang
Nader Bagherzadeh
Publication date
01-08-2015
Publisher
Springer US
Published in
The Journal of Supercomputing / Issue 8/2015
Print ISSN: 0920-8542
Electronic ISSN: 1573-0484
DOI
https://doi.org/10.1007/s11227-014-1341-4

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