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A Robust Architecture Based on Adaptive Recursive Filter for Gigabit Communications Read chapter Read first chapter

2021 | OriginalPaper | Chapter

Design of Low Standby Power 10T SRAM Cell with Improved Write Margin

Authors : R. Manoj Kumar, P. V. Sridevi

Published in: Microelectronics, Electromagnetics and Telecommunications

Publisher: Springer Singapore

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Abstract

There is a growing concern regarding the increased standby power and reduced stability of SRAM due to continued scaling in technology node. So, there is a necessity to design a new SRAM cell which addresses the concerns related to SRAM cell. So, 10T SRAM cell is proposed with reduced standby power and enhanced stability in read, write and hold modes of operation. There is a reduction in standby power because of the usage of stacked transistors. P10T SRAM cell has decreased the standby power while holding 1 by 4.9%, 15.99% and 1.68% compared to 8T, 8TG and 9T respectively at the worst process corner FF at 0.9 V VDD. There is an increase of 262.89, 47.566, 261.75% write margin compared to 6T, 8TG, 9T SRAM cells at 0.9 V supply voltage for TT corner. The influence of process and voltage variations on write margin was studied on available and proposed SRAM cells. All designs are designed using in cadence virtuoso in 45 nm CMOS technology node.

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Metadata
Title
Design of Low Standby Power 10T SRAM Cell with Improved Write Margin
Authors
R. Manoj Kumar
P. V. Sridevi
Copyright Year
2021
Publisher
Springer Singapore
Book
Microelectronics, Electromagnetics and Telecommunications

Print ISBN: 978-981-15-3827-8

Electronic ISBN: 978-981-15-3828-5

Copyright Year: 2021

DOI
https://doi.org/10.1007/978-981-15-3828-5_53