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2015 | OriginalPaper | Chapter

8. Efficient Automated Speedpath Debugging

Authors : Mehdi Dehbashi, Görschwin Fey

Published in: Debug Automation from Pre-Silicon to Post-Silicon

Publisher: Springer International Publishing

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Abstract

There are some approaches which try to reduce the size of the debugging model in order to efficiently localize the root causes of an error. QBF is used in [ASV+05] to reduce the size of the debugging instance. Moreover, the performance and applicability of debugging is improved using MaxSAT which simplifies the formulation of the debugging problem and reduces the size of the debugging instance and the debug time [CSMSV10]. Abstraction and refinement techniques can also handle large designs with a better performance by debugging an abstract model of the circuit [SV07]. The X value (three-valued logic) is used to abstract a circuit for efficient model checking [GSY07]. However, the previous approaches do not consider any timing information of the circuit.

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Literature
[ABD+06]
go back to reference Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, and Dave Miller. A reconfigurable design-for-debug infrastructure for SoCs. In Proceedings of the Design Automation Conference, pages 7–12, 2006. Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, and Dave Miller. A reconfigurable design-for-debug infrastructure for SoCs. In Proceedings of the Design Automation Conference, pages 7–12, 2006.
[ABZ03]
go back to reference Aseem Agarwal, David Blaauw, and Vladimir Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In Proceedings of the International Conference on Computer-Aided Design, pages 900–907, 2003. Aseem Agarwal, David Blaauw, and Vladimir Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In Proceedings of the International Conference on Computer-Aided Design, pages 900–907, 2003.
[Ait97]
go back to reference Robert C Aitken. Modeling the unmodelable: Algorithmic fault diagnosis. IEEE Design & Test of Computers, 14(3):98–103, 1997. Robert C Aitken. Modeling the unmodelable: Algorithmic fault diagnosis. IEEE Design & Test of Computers, 14(3):98–103, 1997.
[AKSN07]
go back to reference Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, and Zainalabedin Navabi. Online NoC switch fault detection and diagnosis using a high level fault mode. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 21–30, 2007. Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, and Zainalabedin Navabi. Online NoC switch fault detection and diagnosis using a high level fault mode. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 21–30, 2007.
[AN07]
go back to reference Ehab Anis and Nicola Nicolici. Low cost debug architecture using lossy compression for silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 1–6, 2007. Ehab Anis and Nicola Nicolici. Low cost debug architecture using lossy compression for silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 1–6, 2007.
[APP10]
go back to reference Massimo Alioto, Gaetano Palumbo, and Melita Pennisi. Understanding the effect of process variations on the delay of static and domino logic. IEEE Transactions on VLSI Systems, 18(5):697–710, 2010.CrossRef Massimo Alioto, Gaetano Palumbo, and Melita Pennisi. Understanding the effect of process variations on the delay of static and domino logic. IEEE Transactions on VLSI Systems, 18(5):697–710, 2010.CrossRef
[ASV+05]
go back to reference Moayad Fahim Ali, Sean Safarpour, Andreas Veneris, Magdy S Abadir, and Rolf Drechsler. Post-verification debugging of hierarchical designs. In Proceedings of the International Conference on Computer-Aided Design, pages 871–876, 2005. Moayad Fahim Ali, Sean Safarpour, Andreas Veneris, Magdy S Abadir, and Rolf Drechsler. Post-verification debugging of hierarchical designs. In Proceedings of the International Conference on Computer-Aided Design, pages 871–876, 2005.
[BBK89]
go back to reference Franc Brglez, David Bryan, and Krzysztof Kozminski. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 1929–1934, 1989. Franc Brglez, David Bryan, and Krzysztof Kozminski. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 1929–1934, 1989.
[BCSS08]
go back to reference David Blaauw, Kaviraj Chopra, Ashish Srivastava, and Louis Scheffer. Statistical timing analysis: From basic principles to state of the art. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(4):589–607, 2008.CrossRef David Blaauw, Kaviraj Chopra, Ashish Srivastava, and Louis Scheffer. Statistical timing analysis: From basic principles to state of the art. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(4):589–607, 2008.CrossRef
[BHvMW09]
go back to reference Armin Biere, Marijn J. H. Heule, Hans van Maaren, and Toby Walsh, editors. Handbook of Satisfiability, volume 185 of Frontiers in Artificial Intelligence and Applications. IOS Press, February 2009. Armin Biere, Marijn J. H. Heule, Hans van Maaren, and Toby Walsh, editors. Handbook of Satisfiability, volume 185 of Frontiers in Artificial Intelligence and Applications. IOS Press, February 2009.
[BKWC08]
go back to reference Pouria Bastani, Kip Killpack, Li-C. Wang, and Eli Chiprout. Speedpath prediction based on learning from a small set of examples. In Proceedings of the Design Automation Conference, pages 217–222, 2008. Pouria Bastani, Kip Killpack, Li-C. Wang, and Eli Chiprout. Speedpath prediction based on learning from a small set of examples. In Proceedings of the Design Automation Conference, pages 217–222, 2008.
[BM02]
go back to reference Luca Benini and Giovanni De Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70–78, 2002. Luca Benini and Giovanni De Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70–78, 2002.
[BPH85]
go back to reference Franc Brglez, Phillip Pownall, and Robert Hum. Accelerated ATPG and fault grading via testability analysis. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 695–698, 1985. Franc Brglez, Phillip Pownall, and Robert Hum. Accelerated ATPG and fault grading via testability analysis. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 695–698, 1985.
[Bre10]
go back to reference Melvin A. Breuer. Hardware that produces bounded rather than exact results. In Proceedings of the Design Automation Conference, pages 871–876, 2010. Melvin A. Breuer. Hardware that produces bounded rather than exact results. In Proceedings of the Design Automation Conference, pages 871–876, 2010.
[Brg85]
go back to reference Franc Brglez. A fast fault grader: Analysis and applications. In Proceedings of the International Test Conference, pages 785–794, 1985. Franc Brglez. A fast fault grader: Analysis and applications. In Proceedings of the International Test Conference, pages 785–794, 1985.
[CAK+09]
go back to reference Caroline Concatto, Pedro Almeida, Fernanda Lima Kastensmidt, Érika F. Cota, Marcelo Lubaszewski, and Marcos Herve. Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults. In IEEE International On-Line Testing Symposium, pages 61–66, 2009. Caroline Concatto, Pedro Almeida, Fernanda Lima Kastensmidt, Érika F. Cota, Marcelo Lubaszewski, and Marcos Herve. Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults. In IEEE International On-Line Testing Symposium, pages 61–66, 2009.
[Car01]
go back to reference John D Carpinelli. Computer systems organization & architecture. Addison-Wesley Boston, San Francisco, New York, 2001. John D Carpinelli. Computer systems organization & architecture. Addison-Wesley Boston, San Francisco, New York, 2001.
[CCLL11]
go back to reference Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, and Chung-Kai Liu. On the design and analysis of fault tolerant NoC architecture using spare routers. In Proceedings of the ASP Design Automation Conference, pages 431–436, 2011. Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, and Chung-Kai Liu. On the design and analysis of fault tolerant NoC architecture using spare routers. In Proceedings of the ASP Design Automation Conference, pages 431–436, 2011.
[CH97]
go back to reference Pi-Yu Chung and Ibrahim N. Hajj. Diagnosis and correction of multiple logic design errors in digital circuits. IEEE Transactions on VLSI Systems, 5(2):233–237, 1997. Pi-Yu Chung and Ibrahim N. Hajj. Diagnosis and correction of multiple logic design errors in digital circuits. IEEE Transactions on VLSI Systems, 5(2):233–237, 1997.
[CKY03]
go back to reference Edmund M. Clarke, Daniel Kroening, and Karen Yorav. Specifying and verifying systems with multiple clocks. In International Conference on Computer Design, pages 48–55, 2003. Edmund M. Clarke, Daniel Kroening, and Karen Yorav. Specifying and verifying systems with multiple clocks. In International Conference on Computer Design, pages 48–55, 2003.
[CMA08]
go back to reference Kypros Constantinides, Onur Mutlu, and Todd M. Austin. Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. In International Symposium on Microarchitecture, pages 282–293, 2008. Kypros Constantinides, Onur Mutlu, and Todd M. Austin. Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. In International Symposium on Microarchitecture, pages 282–293, 2008.
[CMAB09]
go back to reference Kypros Constantinides, Onur Mutlu, Todd M. Austin, and Valeria Bertacco. A flexible software-based framework for online detection of hardware defects. IEEE Transactions Computers, 58(8):1063–1079, 2009. Kypros Constantinides, Onur Mutlu, Todd M. Austin, and Valeria Bertacco. A flexible software-based framework for online detection of hardware defects. IEEE Transactions Computers, 58(8):1063–1079, 2009.
[CMB07a]
go back to reference Kai-Hui Chang, Igor L. Markov, and Valeria Bertacco. Automating post-silicon debugging and repair. In Proceedings of the International Conference on Computer-Aided Design, pages 91–98, 2007. Kai-Hui Chang, Igor L. Markov, and Valeria Bertacco. Automating post-silicon debugging and repair. In Proceedings of the International Conference on Computer-Aided Design, pages 91–98, 2007.
[CMB07b]
go back to reference Kai-Hui Chang, Igor L Markov, and Valeria Bertacco. Fixing design errors with counterexamples and resynthesis. In Proceedings of the ASP Design Automation Conference, pages 944–949, 2007. Kai-Hui Chang, Igor L Markov, and Valeria Bertacco. Fixing design errors with counterexamples and resynthesis. In Proceedings of the ASP Design Automation Conference, pages 944–949, 2007.
[CMR+10]
go back to reference Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, and Srimat T. Chakradhar. Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. In Proceedings of the Design Automation Conference, pages 555–560, 2010. Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, and Srimat T. Chakradhar. Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. In Proceedings of the Design Automation Conference, pages 555–560, 2010.
[CR10]
go back to reference Srimat T. Chakradhar and Anand Raghunathan. Best-effort computing: re-thinking parallel software and hardware. In Proceedings of the Design Automation Conference, pages 865–870, 2010. Srimat T. Chakradhar and Anand Raghunathan. Best-effort computing: re-thinking parallel software and hardware. In Proceedings of the Design Automation Conference, pages 865–870, 2010.
[CSMSV10]
go back to reference Yibin Chen, Sean Safarpour, Joao Marques-Silva, and Andreas Veneris. Automated design debugging with maximum satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(11):1804–1817, 2010.CrossRef Yibin Chen, Sean Safarpour, Joao Marques-Silva, and Andreas Veneris. Automated design debugging with maximum satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(11):1804–1817, 2010.CrossRef
[DF12]
go back to reference Mehdi Dehbashi and Goerschwin Fey. Automated debugging from pre-silicon to post-silicon. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 324–329, 2012. Mehdi Dehbashi and Goerschwin Fey. Automated debugging from pre-silicon to post-silicon. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 324–329, 2012.
[DF13a]
go back to reference Mehdi Dehbashi and Goerschwin Fey. Debug automation for logic circuits under timing variations. IEEE Design & Test of Computers, 30(6):60–69, 2013.CrossRef Mehdi Dehbashi and Goerschwin Fey. Debug automation for logic circuits under timing variations. IEEE Design & Test of Computers, 30(6):60–69, 2013.CrossRef
[DF13b]
go back to reference Mehdi Dehbashi and Goerschwin Fey. Efficient automated speedpath debugging. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 48–53, 2013. Mehdi Dehbashi and Goerschwin Fey. Efficient automated speedpath debugging. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 48–53, 2013.
[DF14a]
go back to reference Mehdi Dehbashi and Goerschwin Fey. Debug automation for synchronization bugs at RTL. In Proceedings of the International Conference on VLSI Design, 2014. Mehdi Dehbashi and Goerschwin Fey. Debug automation for synchronization bugs at RTL. In Proceedings of the International Conference on VLSI Design, 2014.
[DF14b]
go back to reference Mehdi Dehbashi and Goerschwin Fey. Transaction-based online debug for NoC-based multiprocessor SoCs. In Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2014. Mehdi Dehbashi and Goerschwin Fey. Transaction-based online debug for NoC-based multiprocessor SoCs. In Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2014.
[DFRR12]
go back to reference Mehdi Dehbashi, Goerschwin Fey, Kaushik Roy, and Anand Raghunathan. On modeling and evaluation of logic circuits under timing variations. In EUROMICRO Symp. on Digital System Design, pages 431–436, 2012. Mehdi Dehbashi, Goerschwin Fey, Kaushik Roy, and Anand Raghunathan. On modeling and evaluation of logic circuits under timing variations. In EUROMICRO Symp. on Digital System Design, pages 431–436, 2012.
[dKK03]
go back to reference Johan de Kleer and James Kurien. Fundamentals of model-based diagnosis. In IFAC Symposium on Fault Detection, Supervision, and Safety of Technical Processes, pages 25–36, 2003. Johan de Kleer and James Kurien. Fundamentals of model-based diagnosis. In IFAC Symposium on Fault Detection, Supervision, and Safety of Technical Processes, pages 25–36, 2003.
[dPNN+11]
go back to reference Flavio M. de Paula, Amir Nahir, Ziv Nevo, Avigal Orni, and Alan J. Hu. TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead. In Proceedings of the Design Automation Conference, pages 411–416, 2011. Flavio M. de Paula, Amir Nahir, Ziv Nevo, Avigal Orni, and Alan J. Hu. TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead. In Proceedings of the Design Automation Conference, pages 411–416, 2011.
[DSF11]
go back to reference Mehdi Dehbashi, André Sülflow, and Goerschwin Fey. Automated design debugging in a testbench-based verification environment. In EUROMICRO Symp. on Digital System Design, pages 479–486, 2011. Mehdi Dehbashi, André Sülflow, and Goerschwin Fey. Automated design debugging in a testbench-based verification environment. In EUROMICRO Symp. on Digital System Design, pages 479–486, 2011.
[DSF13]
go back to reference Mehdi Dehbashi, André Sülflow, and Goerschwin Fey. Automated design debugging in a testbench-based verification environment. Microprocessors and Microsystems, 37(2):206–217, 2013.CrossRef Mehdi Dehbashi, André Sülflow, and Goerschwin Fey. Automated design debugging in a testbench-based verification environment. Microprocessors and Microsystems, 37(2):206–217, 2013.CrossRef
[EEH+06]
go back to reference Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, and Michael Velten. Requirements and concepts for transaction level assertions. In International Conference on Computer Design, 2006. Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, and Michael Velten. Requirements and concepts for transaction level assertions. In International Conference on Computer Design, 2006.
[EKD+03]
go back to reference Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, and Trevor N. Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In International Symposium on Microarchitecture, pages 7–18, 2003. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, and Trevor N. Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In International Symposium on Microarchitecture, pages 7–18, 2003.
[ES04]
go back to reference Niklas Eén and Niklas Sörensson. An extensible SAT solver. In Proceedings of the International Conference on Theory and Applications of Satisfiability Testing, volume 2919 of Lecture Notes in Computer Science, pages 502–518, 2004. Niklas Eén and Niklas Sörensson. An extensible SAT solver. In Proceedings of the International Conference on Theory and Applications of Satisfiability Testing, volume 2919 of Lecture Notes in Computer Science, pages 502–518, 2004.
[FAVS+04]
go back to reference M Fahim Ali, Andreas Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, and Magdy Abadir. Debugging sequential circuits using Boolean satisfiability. In Proceedings of the International Conference on Computer-Aided Design, pages 204–209, 2004. M Fahim Ali, Andreas Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, and Magdy Abadir. Debugging sequential circuits using Boolean satisfiability. In Proceedings of the International Conference on Computer-Aided Design, pages 204–209, 2004.
[FD05]
go back to reference Goerschwin Fey and Rolf Drechsler. Efficient hierarchical system debugging for property checking. In In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2005, pages 41–46, 2005. Goerschwin Fey and Rolf Drechsler. Efficient hierarchical system debugging for property checking. In In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2005, pages 41–46, 2005.
[FSBD08]
go back to reference Goerschwin Fey, Stefan Staber, Roderick Bloem, and Rolf Drechsler. Automatic fault localization for property checking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6):1138–1149, 2008.CrossRef Goerschwin Fey, Stefan Staber, Roderick Bloem, and Rolf Drechsler. Automatic fault localization for property checking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6):1138–1149, 2008.CrossRef
[FSW99]
go back to reference Gerhard Friedrich, Markus Stumptner, and Franz Wotawa. Model-based diagnosis of hardware designs. Artificial Intelligence, 111(1–2):3–39, 1999.MathSciNetCrossRefMATH Gerhard Friedrich, Markus Stumptner, and Franz Wotawa. Model-based diagnosis of hardware designs. Artificial Intelligence, 111(1–2):3–39, 1999.MathSciNetCrossRefMATH
[GF09]
go back to reference Amir Masoud Gharehbaghi and Masahiro Fujita. Transaction-based debugging of system-on-chips with patterns. In International Conference on Computer Design, pages 186–192, 2009. Amir Masoud Gharehbaghi and Masahiro Fujita. Transaction-based debugging of system-on-chips with patterns. In International Conference on Computer Design, pages 186–192, 2009.
[GF12]
go back to reference Amir Masoud Gharehbaghi and Masahiro Fujita. Transaction-based post-silicon debug of many-core system-on-chips. In Proceedings of the International Symposium on Quality Electronic Design, pages 702–708, 2012. Amir Masoud Gharehbaghi and Masahiro Fujita. Transaction-based post-silicon debug of many-core system-on-chips. In Proceedings of the International Symposium on Quality Electronic Design, pages 702–708, 2012.
[GG07]
go back to reference Malay K. Ganai and Aarti Gupta. Efficient BMC for multi-clock systems with clocked specifications. In Proceedings of the ASP Design Automation Conference, pages 310–315, 2007. Malay K. Ganai and Aarti Gupta. Efficient BMC for multi-clock systems with clocked specifications. In Proceedings of the ASP Design Automation Conference, pages 310–315, 2007.
[GK05]
go back to reference Alex Groce and Daniel Kroening. Making the most of BMC counterexamples. Electronic Notes in Theoretical Computer Science, 119(2):67–81, 2005.CrossRef Alex Groce and Daniel Kroening. Making the most of BMC counterexamples. Electronic Notes in Theoretical Computer Science, 119(2):67–81, 2005.CrossRef
[GK10]
go back to reference Kunal P. Ganeshpure and Sandip Kundu. On ATPG for multiple aggressor crosstalk faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(5):774–787, 2010. Kunal P. Ganeshpure and Sandip Kundu. On ATPG for multiple aggressor crosstalk faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(5):774–787, 2010.
[GMK91]
go back to reference Torsten Grüning, Udo Mahlstedt, and Hartmut Koopmeiners. DIATEST: A fast diagnostic test pattern generator for combinational circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 194–197, 1991. Torsten Grüning, Udo Mahlstedt, and Hartmut Koopmeiners. DIATEST: A fast diagnostic test pattern generator for combinational circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 194–197, 1991.
[GMP+11]
go back to reference Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, and Kaushik Roy. IMPACT: imprecise adders for low-power approximate computing. In International Symposium on Low Power Electronics and Design, pages 409–414, 2011. Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, and Kaushik Roy. IMPACT: imprecise adders for low-power approximate computing. In International Symposium on Low Power Electronics and Design, pages 409–414, 2011.
[GPS+12]
go back to reference Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, and Valeria Bertacco. Comprehensive online defect diagnosis in on-chip networks. In Proceedings of the VLSI Test Symposium, pages 44–49, 2012. Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, and Valeria Bertacco. Comprehensive online defect diagnosis in on-chip networks. In Proceedings of the VLSI Test Symposium, pages 44–49, 2012.
[GSY07]
go back to reference Orna Grumberg, Assaf Schuster, and Avi Yadgar. 3-valued circuit SAT for STE with automatic refinement. In Automated Technology for Verification and Analysis, pages 457–473, 2007. Orna Grumberg, Assaf Schuster, and Avi Yadgar. 3-valued circuit SAT for STE with automatic refinement. In Automated Technology for Verification and Analysis, pages 457–473, 2007.
[Gup07]
go back to reference Aarti Gupta. SAT-based scalable formal verification solutions. Springer, 2007. Aarti Gupta. SAT-based scalable formal verification solutions. Springer, 2007.
[GVVSB07]
go back to reference Kees Goossens, Bart Vermeulen, Remco Van Steeden, and Martijn Bennebroek. Transaction-based communication-centric debug. In International Symposium on Networks-on-Chips, pages 95–106, 2007. Kees Goossens, Bart Vermeulen, Remco Van Steeden, and Martijn Bennebroek. Transaction-based communication-centric debug. In International Symposium on Networks-on-Chips, pages 95–106, 2007.
[GYP+10]
go back to reference Mingzhi Gao, Zuochang Ye, Yao Peng, Yan Wang, and Zhiping Yu. A comprehensive model for gate delay under process variation and different driving and loading conditions. In Proceedings of the International Symposium on Quality Electronic Design, pages 406–412, 2010. Mingzhi Gao, Zuochang Ye, Yao Peng, Yan Wang, and Zhiping Yu. A comprehensive model for gate delay under process variation and different driving and loading conditions. In Proceedings of the International Symposium on Quality Electronic Design, pages 406–412, 2010.
[Hay85]
go back to reference John P. Hayes. Fault modeling. IEEE Design & Test of Computers, pages 37–44, 1985. John P. Hayes. Fault modeling. IEEE Design & Test of Computers, pages 37–44, 1985.
[HMM06]
go back to reference Andrew B. T. Hopkins and Klaus D. McDonald-Maier. Debug support for complex systems on-chip: a review. IEE Proceedings on Computers and Digital Techniques, 153(4):197 – 207, 2006. Andrew B. T. Hopkins and Klaus D. McDonald-Maier. Debug support for complex systems on-chip: a review. IEE Proceedings on Computers and Digital Techniques, 153(4):197 – 207, 2006.
[IEE05]
go back to reference IEEE. IEEE Std 1850–2005 – IEEE Standard for Property Specification Language (PSL). The IEEE, 2005. IEEE. IEEE Std 1850–2005 – IEEE Standard for Property Specification Language (PSL). The IEEE, 2005.
[JLJ09]
go back to reference Tai-Ying Jiang, C-NJ Liu, and Jing-Yang Jou. Accurate rank ordering of error candidates for efficient HDL design debugging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):272–284, 2009. Tai-Ying Jiang, C-NJ Liu, and Jing-Yang Jou. Accurate rank ordering of error candidates for efficient HDL design debugging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):272–284, 2009.
[KKC07]
go back to reference Kip Killpack, Chandramouli V. Kashyap, and Eli Chiprout. Silicon speedpath measurement and feedback into EDA flows. In Proceedings of the Design Automation Conference, pages 390–395, 2007. Kip Killpack, Chandramouli V. Kashyap, and Eli Chiprout. Silicon speedpath measurement and feedback into EDA flows. In Proceedings of the Design Automation Conference, pages 390–395, 2007.
[KKKS10]
go back to reference Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori. Slack redistribution for graceful degradation under voltage overscaling. In Proceedings of the ASP Design Automation Conference, pages 825–831, 2010. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori. Slack redistribution for graceful degradation under voltage overscaling. In Proceedings of the ASP Design Automation Conference, pages 825–831, 2010.
[KM03]
go back to reference JA Knottnerus and JW Muris. Assessment of the accuracy of diagnostic tests: the cross-sectional study. Journal of Clinical Epidemiology, 56(11):1118–1128, 2003. JA Knottnerus and JW Muris. Assessment of the accuracy of diagnostic tests: the cross-sectional study. Journal of Clinical Epidemiology, 56(11):1118–1128, 2003.
[KN08]
go back to reference Ho Fai Ko and Nicola Nicolici. Automated trace signals identification and state restoration for improving observability in post-silicon validation. In Proceedings of Design, Automation and Test in Europe, pages 1298–1303, 2008. Ho Fai Ko and Nicola Nicolici. Automated trace signals identification and state restoration for improving observability in post-silicon validation. In Proceedings of Design, Automation and Test in Europe, pages 1298–1303, 2008.
[KNKB08]
go back to reference Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, and Pouria Bastani. Case study on speed failure causes in a microprocessor. IEEE Design & Test of Computers, 25(3):224–230, 2008.CrossRef Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, and Pouria Bastani. Case study on speed failure causes in a microprocessor. IEEE Design & Test of Computers, 25(3):224–230, 2008.CrossRef
[Lar92]
go back to reference Tracy Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(1): 4–15, 1992.CrossRef Tracy Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(1): 4–15, 1992.CrossRef
[LCB+10]
go back to reference Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, and Subhasish Mitra. ERSA: Error resilient system architecture for probabilistic applications. In Proceedings of Design, Automation and Test in Europe, pages 1560–1565, 2010. Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, and Subhasish Mitra. ERSA: Error resilient system architecture for probabilistic applications. In Proceedings of Design, Automation and Test in Europe, pages 1560–1565, 2010.
[LDX12]
go back to reference Min Li, Azadeh Davoodi, and Lin Xie. Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. In Proceedings of Design, Automation and Test in Europe, pages 1591–1596, 2012. Min Li, Azadeh Davoodi, and Lin Xie. Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. In Proceedings of Design, Automation and Test in Europe, pages 1591–1596, 2012.
[LEN+11]
go back to reference Avinash Lingamneni, Christian Enz, Jean-Luc Nagel, Krishna Palem, and Christian Piguet. Energy parsimonious circuit design through probabilistic pruning. In Proceedings of Design, Automation and Test in Europe, pages 764–769, 2011. Avinash Lingamneni, Christian Enz, Jean-Luc Nagel, Krishna Palem, and Christian Piguet. Energy parsimonious circuit design through probabilistic pruning. In Proceedings of Design, Automation and Test in Europe, pages 764–769, 2011.
[LGD12]
go back to reference Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic TLM fault localization for SystemC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(8):1249–1262, 2012. Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic TLM fault localization for SystemC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(8):1249–1262, 2012.
[LLC07]
go back to reference Yung-Chieh Lin, Feng Lu, and Kwang-Ting Cheng. Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(5):932–942, 2007.CrossRef Yung-Chieh Lin, Feng Lu, and Kwang-Ting Cheng. Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(5):932–942, 2007.CrossRef
[LMF11]
go back to reference Yeonbok Lee, Takeshi Matsumoto, and Masahiro Fujita. On-chip dynamic signal sequence slicing for efficient post-silicon debugging. In Proceedings of the ASP Design Automation Conference, pages 719–724, 2011. Yeonbok Lee, Takeshi Matsumoto, and Masahiro Fujita. On-chip dynamic signal sequence slicing for efficient post-silicon debugging. In Proceedings of the ASP Design Automation Conference, pages 719–724, 2011.
[LRS89]
go back to reference Wing-Ning Li, Sudhakar M Reddy, and Sartaj K Sahni. On path selection in combinational logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56–63, 1989. Wing-Ning Li, Sudhakar M Reddy, and Sartaj K Sahni. On path selection in combinational logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56–63, 1989.
[LS80]
go back to reference Jean Davies Lesser and John J. Shedletsky. An experimental delay test generator for LSI logic. IEEE Transactions on Computers, 100(3):235–248, 1980. Jean Davies Lesser and John J. Shedletsky. An experimental delay test generator for LSI logic. IEEE Transactions on Computers, 100(3):235–248, 1980.
[LV05]
go back to reference Jiang Brandon Liu and Andreas Veneris. Incremental fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(2): 240–251, 2005. Jiang Brandon Liu and Andreas Veneris. Incremental fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(2): 240–251, 2005.
[LWPM05]
go back to reference Leonard Lee, Li-C. Wang, Praveen Parvathala, and T. M. Mak. On silicon-based speed path identification. In Proceedings of the VLSI Test Symposium, pages 35–41, 2005. Leonard Lee, Li-C. Wang, Praveen Parvathala, and T. M. Mak. On silicon-based speed path identification. In Proceedings of the VLSI Test Symposium, pages 35–41, 2005.
[LX10]
go back to reference Xiao Liu and Qiang Xu. On signal tracing for debugging speedpath-related electrical errors in post-silicon validation. In Proceedings of the IEEE Asian Test Symposium, pages 243–248, 2010. Xiao Liu and Qiang Xu. On signal tracing for debugging speedpath-related electrical errors in post-silicon validation. In Proceedings of the IEEE Asian Test Symposium, pages 243–248, 2010.
[Mal87]
go back to reference Wojciech Maly. Realistic fault modeling for VLSI testing. In Proceedings of the Design Automation Conference, pages 173–180. ACM, 1987. Wojciech Maly. Realistic fault modeling for VLSI testing. In Proceedings of the Design Automation Conference, pages 173–180. ACM, 1987.
[MB91]
go back to reference Patrick C McGeer and Robert K Brayton. Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Kluwer Academic Publishers, 1991. Patrick C McGeer and Robert K Brayton. Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Kluwer Academic Publishers, 1991.
[MCRR11]
go back to reference Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, and Kaushik Roy. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of Design, Automation and Test in Europe, pages 950–955, 2011. Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, and Kaushik Roy. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of Design, Automation and Test in Europe, pages 950–955, 2011.
[MJR86]
go back to reference Yashwant K Malaiya, AP Jayasumana, and R Rajsuman. A detailed examination of bridging faults. In International Conference on Computer Design, pages 78–81, 1986. Yashwant K Malaiya, AP Jayasumana, and R Rajsuman. A detailed examination of bridging faults. In International Conference on Computer Design, pages 78–81, 1986.
[MMSTR09]
go back to reference Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, and Janusz Rajski. Timing-aware multiple-delay-fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):245–258, 2009. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, and Janusz Rajski. Timing-aware multiple-delay-fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):245–258, 2009.
[MS95]
go back to reference Joao Marques-Silva. Search algorithms for satisfiability problems in combinational switching circuits. PhD thesis, University of Michigan, 1995. Joao Marques-Silva. Search algorithms for satisfiability problems in combinational switching circuits. PhD thesis, University of Michigan, 1995.
[MS07]
go back to reference Wolfgang Mayer and Markus Stumptner. Model-based debugging–state of the art and future challenges. Electronic Notes in Theoretical Computer Science, 174(4): 61–82, 2007.CrossRef Wolfgang Mayer and Markus Stumptner. Model-based debugging–state of the art and future challenges. Electronic Notes in Theoretical Computer Science, 174(4): 61–82, 2007.CrossRef
[MVL09]
go back to reference Richard McLaughlin, Srikanth Venkataraman, and Carlston Lim. Automated debug of speed path failures using functional tests. In Proceedings of the VLSI Test Symposium, pages 91–96, 2009. Richard McLaughlin, Srikanth Venkataraman, and Carlston Lim. Automated debug of speed path failures using functional tests. In Proceedings of the VLSI Test Symposium, pages 91–96, 2009.
[MVS+07]
go back to reference Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Farid N Najm, and Magdy S Abadir. Maximum circuit activity estimation using pseudo-boolean satisfiability. In Proceedings of Design, Automation and Test in Europe, pages 1538–1543, 2007. Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Farid N Najm, and Magdy S Abadir. Maximum circuit activity estimation using pseudo-boolean satisfiability. In Proceedings of Design, Automation and Test in Europe, pages 1538–1543, 2007.
[OHN09]
go back to reference Sari Onaissi, Khaled R. Heloue, and Farid N. Najm. PSTA-based branch and bound approach to the silicon speedpath isolation problem. In Proceedings of the International Conference on Computer-Aided Design, pages 217–224, 2009. Sari Onaissi, Khaled R. Heloue, and Farid N. Najm. PSTA-based branch and bound approach to the silicon speedpath isolation problem. In Proceedings of the International Conference on Computer-Aided Design, pages 217–224, 2009.
[PGI+05]
go back to reference Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, and Giovanni De Micheli. Design, synthesis, and test of networks on chips. IEEE Design & Test of Computers, 22(5):404–413, 2005. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, and Giovanni De Micheli. Design, synthesis, and test of networks on chips. IEEE Design & Test of Computers, 22(5):404–413, 2005.
[PGSR10]
go back to reference Mihalis Psarakis, Dimitris Gizopoulos, Edgar Sánchez, and Matteo Sonza Reorda. Microprocessor software-based self-testing. IEEE Design & Test of Computers, 27(3):4–19, 2010. Mihalis Psarakis, Dimitris Gizopoulos, Edgar Sánchez, and Matteo Sonza Reorda. Microprocessor software-based self-testing. IEEE Design & Test of Computers, 27(3):4–19, 2010.
[PHM09]
go back to reference Sung-Boem Park, Ted Hong, and Subhasish Mitra. Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10): 1545–1558, 2009.CrossRef Sung-Boem Park, Ted Hong, and Subhasish Mitra. Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10): 1545–1558, 2009.CrossRef
[QW03]
go back to reference Wangqi Qiu and D. M. H. Walker. An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit. In Proceedings of the International Test Conference, pages 592–601, 2003. Wangqi Qiu and D. M. H. Walker. An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit. In Proceedings of the International Test Conference, pages 592–601, 2003.
[RGU09]
go back to reference Jaan Raik, Vineeth Govind, and Raimund Ubar. Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Computers & Digital Techniques, 3(5):476–486, 2009.CrossRef Jaan Raik, Vineeth Govind, and Raimund Ubar. Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Computers & Digital Techniques, 3(5):476–486, 2009.CrossRef
[RS04]
go back to reference Kavita Ravi and Fabio Somenzi. Minimal assignments for bounded model checking. In Tools and Algorithms for the Construction and Analysis of Systems, volume 2988 of LNCS, pages 31–45, 2004. Kavita Ravi and Fabio Somenzi. Minimal assignments for bounded model checking. In Tools and Algorithms for the Construction and Analysis of Systems, volume 2988 of LNCS, pages 31–45, 2004.
[SAKJ10]
go back to reference Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, and Douglas L. Jones. Stochastic computation. In Proceedings of the Design Automation Conference, pages 859–864, 2010. Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, and Douglas L. Jones. Stochastic computation. In Proceedings of the Design Automation Conference, pages 859–864, 2010.
[SCPB12]
go back to reference Matthias Sauer, Alexander Czutro, Ilia Polian, and Bernd Becker. Small-delay-fault ATPG with waveform accuracy. In Proceedings of the International Conference on Computer-Aided Design, pages 30–36, 2012. Matthias Sauer, Alexander Czutro, Ilia Polian, and Bernd Becker. Small-delay-fault ATPG with waveform accuracy. In Proceedings of the International Conference on Computer-Aided Design, pages 30–36, 2012.
[SD10]
go back to reference André Sülflow and Rolf Drechsler. Automatic fault localization for programmable logic controllers. In Formal Methods for Automation and Safety in Railway and Automotive Systems, pages 247–256, 2010. André Sülflow and Rolf Drechsler. Automatic fault localization for programmable logic controllers. In Formal Methods for Automation and Safety in Railway and Automotive Systems, pages 247–256, 2010.
[SFB+09]
go back to reference André Sülflow, Goerschwin Fey, Cécile Braunstein, Ulrich Kühne, and Rolf Drechsler. Increasing the accuracy of SAT-based debugging. In Proceedings of Design, Automation and Test in Europe, pages 1326–1332, 2009. André Sülflow, Goerschwin Fey, Cécile Braunstein, Ulrich Kühne, and Rolf Drechsler. Increasing the accuracy of SAT-based debugging. In Proceedings of Design, Automation and Test in Europe, pages 1326–1332, 2009.
[SFBD08]
go back to reference André Sülflow, Goerschwin Fey, Roderick Bloem, and Rolf Drechsler. Using unsatisfiable cores to debug multiple design errors. In Great Lakes Symposium VLSI, pages 77–82, 2008. André Sülflow, Goerschwin Fey, Roderick Bloem, and Rolf Drechsler. Using unsatisfiable cores to debug multiple design errors. In Great Lakes Symposium VLSI, pages 77–82, 2008.
[SFD10]
go back to reference André Sülflow, Goerschwin Fey, and Rolf Drechsler. Using QBF to increase accuracy of SAT-based debugging. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 641–644, 2010. André Sülflow, Goerschwin Fey, and Rolf Drechsler. Using QBF to increase accuracy of SAT-based debugging. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 641–644, 2010.
[SG10]
go back to reference Doochul Shin and Sandeep K. Gupta. Approximate logic synthesis for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 957–960, 2010. Doochul Shin and Sandeep K. Gupta. Approximate logic synthesis for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 957–960, 2010.
[SG11]
go back to reference Doochul Shin and Sandeep K. Gupta. A new circuit simplification method for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 1566–1571, 2011. Doochul Shin and Sandeep K. Gupta. A new circuit simplification method for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 1566–1571, 2011.
[SGC11]
go back to reference Saeed Shamshiri, Amirali Ghofrani, and Kwang-Ting Cheng. End-to-end error correction and online diagnosis for on-chip networks. In Proceedings of the International Test Conference, pages 1–10, 2011. Saeed Shamshiri, Amirali Ghofrani, and Kwang-Ting Cheng. End-to-end error correction and online diagnosis for on-chip networks. In Proceedings of the International Test Conference, pages 1–10, 2011.
[SGT+08]
go back to reference Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari, and Josep Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions Semiconductor Manufacturing, 21(1): 3–13, 2008. Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari, and Josep Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions Semiconductor Manufacturing, 21(1): 3–13, 2008.
[SGTT08]
go back to reference Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas. EVAL: Utilizing processors with variation-induced timing errors. In International Symposium on Microarchitecture, pages 423–434, 2008. Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas. EVAL: Utilizing processors with variation-induced timing errors. In International Symposium on Microarchitecture, pages 423–434, 2008.
[SKF+09]
go back to reference André Sülflow, Ulrich Kuhne, Goerschwin Fey, Daniel Grosse, and Rolf Drechsler. WoLFram – a word level framework for formal verification. In IEEE/IFIP International Symposium on Rapid System Prototyping, pages 11–17, 2009. André Sülflow, Ulrich Kuhne, Goerschwin Fey, Daniel Grosse, and Rolf Drechsler. WoLFram – a word level framework for formal verification. In IEEE/IFIP International Symposium on Rapid System Prototyping, pages 11–17, 2009.
[SRL+11]
go back to reference Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, and Davide Bertozzi. Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In Proceedings of Design, Automation and Test in Europe, pages 661–666, 2011. Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, and Davide Bertozzi. Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In Proceedings of Design, Automation and Test in Europe, pages 661–666, 2011.
[SV07]
go back to reference Sean Safarpour and Andreas Veneris. Abstraction and refinement techniques in automated design debugging. In Proceedings of Design, Automation and Test in Europe, pages 1182–1187, 2007. Sean Safarpour and Andreas Veneris. Abstraction and refinement techniques in automated design debugging. In Proceedings of Design, Automation and Test in Europe, pages 1182–1187, 2007.
[SVAV05]
go back to reference Alexander Smith, Andreas Veneris, Moayad Fahim Ali, and Anastasios Viglas. Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(10):1606–1621, 2005. Alexander Smith, Andreas Veneris, Moayad Fahim Ali, and Anastasios Viglas. Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(10):1606–1621, 2005.
[SVD08]
go back to reference Sean Safarpour, Andreas G Veneris, and Rolf Drechsler. Improved SAT-based reachability analysis with observability don’t cares. Journal of Satisfiability, Boolean Modeling and Computation, 5:1–25, 2008. Sean Safarpour, Andreas G Veneris, and Rolf Drechsler. Improved SAT-based reachability analysis with observability don’t cares. Journal of Satisfiability, Boolean Modeling and Computation, 5:1–25, 2008.
[TBG11]
go back to reference Desta Tadesse, R. Iris Bahar, and Joel Grodstein. Test vector generation for post-silicon delay testing using SAT-based decision problems. Journal of Electronic Testing: Theory and Applications, 27(2):123–136, 2011. Desta Tadesse, R. Iris Bahar, and Joel Grodstein. Test vector generation for post-silicon delay testing using SAT-based decision problems. Journal of Electronic Testing: Theory and Applications, 27(2):123–136, 2011.
[TBW+09]
go back to reference James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, and Tanay Karnik. Resilient circuits - enabling energy-efficient performance and reliability. In Proceedings of the International Conference on Computer-Aided Design, pages 71–73, 2009. James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, and Tanay Karnik. Resilient circuits - enabling energy-efficient performance and reliability. In Proceedings of the International Conference on Computer-Aided Design, pages 71–73, 2009.
[TGR+12]
go back to reference Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, and Ulf Schlichtmann. Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs. In International Conference on Hardware/Software Codesign and System Synthesis, pages 181–186, 2012. Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, and Ulf Schlichtmann. Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs. In International Conference on Hardware/Software Codesign and System Synthesis, pages 181–186, 2012.
[THPM+10]
go back to reference Yanjing Li Ted Hong, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, and Subhasish Mitra. QED: Quick error detection tests for effective post-silicon validation. In Proceedings of the International Test Conference, pages 1–10, 2010. Yanjing Li Ted Hong, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, and Subhasish Mitra. QED: Quick error detection tests for effective post-silicon validation. In Proceedings of the International Test Conference, pages 1–10, 2010.
[Tse68]
go back to reference Grigori S Tseitin. On the complexity of derivation in the propositional calculus. Zapiski nauchnykh seminarov LOMI, 8:234–259, 1968. Grigori S Tseitin. On the complexity of derivation in the propositional calculus. Zapiski nauchnykh seminarov LOMI, 8:234–259, 1968.
[TX07]
go back to reference Shan Tang and Qiang Xu. A multi-core debug platform for NoC-based systems. In Proceedings of Design, Automation and Test in Europe, pages 870–875, 2007. Shan Tang and Qiang Xu. A multi-core debug platform for NoC-based systems. In Proceedings of Design, Automation and Test in Europe, pages 870–875, 2007.
[VARR11]
go back to reference Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, and Anand Raghunathan. MACACO: Modeling and analysis of circuits for approximate computing. In Proceedings of the International Conference on Computer-Aided Design, pages 667–673, 2011. Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, and Anand Raghunathan. MACACO: Modeling and analysis of circuits for approximate computing. In Proceedings of the International Conference on Computer-Aided Design, pages 667–673, 2011.
[Vel05]
go back to reference Miroslav N Velev. Comparison of schemes for encoding unobservability in translation to SAT. In Proceedings of the ASP Design Automation Conference, pages 1056–1059, 2005. Miroslav N Velev. Comparison of schemes for encoding unobservability in translation to SAT. In Proceedings of the ASP Design Automation Conference, pages 1056–1059, 2005.
[Ver02]
go back to reference SystemC Version. 2.0 user’s guide. Open SystemC Initiative, 2002. SystemC Version. 2.0 user’s guide. Open SystemC Initiative, 2002.
[VG09]
go back to reference Bart Vermeulen and Kees Goossens. A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs. In International Symposium on VLSI Design, Automation and Test, pages 183–186, 2009. Bart Vermeulen and Kees Goossens. A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs. In International Symposium on VLSI Design, Automation and Test, pages 183–186, 2009.
[VH99]
go back to reference Andreas Veneris and Ibrahim N Hajj. Design error diagnosis and correction via test vector simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1803–1816, 1999. Andreas Veneris and Ibrahim N Hajj. Design error diagnosis and correction via test vector simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1803–1816, 1999.
[VWB02]
go back to reference Baart Vermeulen, Tom Waayers, and Sjaak Bakker. IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips. In Proceedings of the International Test Conference, pages 55–63, 2002. Baart Vermeulen, Tom Waayers, and Sjaak Bakker. IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips. In Proceedings of the International Test Conference, pages 55–63, 2002.
[VWG02]
go back to reference Bart Vermeulen, Tom Waayers, and Sandeep Kumar Goel. Core-based scan architecture for silicon debug. In Proceedings of the International Test Conference, pages 638–647, 2002. Bart Vermeulen, Tom Waayers, and Sandeep Kumar Goel. Core-based scan architecture for silicon debug. In Proceedings of the International Test Conference, pages 638–647, 2002.
[WC09]
go back to reference Lu Wan and Deming Chen. Dynatune: Circuit-level optimization for timing speculation considering dynamic path behavior. In Proceedings of the International Conference on Computer-Aided Design, pages 172–179, 2009. Lu Wan and Deming Chen. Dynatune: Circuit-level optimization for timing speculation considering dynamic path behavior. In Proceedings of the International Conference on Computer-Aided Design, pages 172–179, 2009.
[WCCC12]
go back to reference Chi-Neng Wen, Shu-Hsuan Chou, Chien-Chih Chen, and Tien-Fu Chen. NUDA: A non-uniform debugging architecture and nonintrusive race detection for many-core systems. IEEE Transactions Computers, 61(2):199–212, 2012.MathSciNetCrossRef Chi-Neng Wen, Shu-Hsuan Chou, Chien-Chih Chen, and Tien-Fu Chen. NUDA: A non-uniform debugging architecture and nonintrusive race detection for many-core systems. IEEE Transactions Computers, 61(2):199–212, 2012.MathSciNetCrossRef
[WLRI87]
go back to reference John A Waicukauski, Eric Lindbloom, Barry K Rosen, and Vijay S Iyengar. Transition fault simulation. IEEE Design & Test of Computers, 4(2):32–38, 1987. John A Waicukauski, Eric Lindbloom, Barry K Rosen, and Vijay S Iyengar. Transition fault simulation. IEEE Design & Test of Computers, 4(2):32–38, 1987.
[XD10]
go back to reference Lin Xie and Azadeh Davoodi. Representative path selection for post-silicon timing prediction under variability. In Proceedings of the Design Automation Conference, pages 386–391, 2010. Lin Xie and Azadeh Davoodi. Representative path selection for post-silicon timing prediction under variability. In Proceedings of the Design Automation Conference, pages 386–391, 2010.
[XD11]
go back to reference Lin Xie and Azadeh Davoodi. Bound-based statistically-critical path extraction under process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(1):59–71, 2011.CrossRef Lin Xie and Azadeh Davoodi. Bound-based statistically-critical path extraction under process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(1):59–71, 2011.CrossRef
[XDS10]
go back to reference Lin Xie, Azadeh Davoodi, and Kewal K. Saluja. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. In Proceedings of the Design Automation Conference, pages 274–279, 2010. Lin Xie, Azadeh Davoodi, and Kewal K. Saluja. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. In Proceedings of the Design Automation Conference, pages 274–279, 2010.
[YNV09]
go back to reference Yu-Shen Yang, Nicola Nicolici, and Andreas G. Veneris. Automated data analysis solutions to silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 982–987, 2009. Yu-Shen Yang, Nicola Nicolici, and Andreas G. Veneris. Automated data analysis solutions to silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 982–987, 2009.
[YPK10]
go back to reference Hyunbean Yi, Sungju Park, and Sandip Kundu. On-chip support for NoC-based SoC debugging. IEEE Transactions on Circuits and Systems, 57-I(7):1608–1617, 2010.MathSciNet Hyunbean Yi, Sungju Park, and Sandip Kundu. On-chip support for NoC-based SoC debugging. IEEE Transactions on Circuits and Systems, 57-I(7):1608–1617, 2010.MathSciNet
[YT08]
go back to reference Joon-Sung Yang and Nur A. Touba. Expanding trace buffer observation window for in-system silicon debug through selective capture. In Proceedings of the VLSI Test Symposium, pages 345–351, 2008. Joon-Sung Yang and Nur A. Touba. Expanding trace buffer observation window for in-system silicon debug through selective capture. In Proceedings of the VLSI Test Symposium, pages 345–351, 2008.
[YT13]
go back to reference Joon-Sung Yang and Nur A Touba. Improved trace buffer observation via selective data capture using 2-d compaction for post-silicon debug. Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 21(2):320–328, 2013. Joon-Sung Yang and Nur A Touba. Improved trace buffer observation via selective data capture using 2-d compaction for post-silicon debug. Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 21(2):320–328, 2013.
[ZCY+07]
go back to reference Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, and Ziyad Hanna. An efficient diagnostic test pattern generation framework using boolean satisfiability. In Proceedings of the ASP Design Automation Conference, pages 288–294, 2007. Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, and Ziyad Hanna. An efficient diagnostic test pattern generation framework using boolean satisfiability. In Proceedings of the ASP Design Automation Conference, pages 288–294, 2007.
[ZGC+10]
go back to reference Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, and Ken Amstutz. Scan based speed-path debug for a microprocessor. In European Test Symposium, pages 207–212, 2010. Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, and Ken Amstutz. Scan based speed-path debug for a microprocessor. In European Test Symposium, pages 207–212, 2010.
Metadata
Title
Efficient Automated Speedpath Debugging
Authors
Mehdi Dehbashi
Görschwin Fey
Copyright Year
2015
DOI
https://doi.org/10.1007/978-3-319-09309-3_8