Influence of the IC power supply and decoupling capacitor arrangement on the electromagnetic emission

The EMC of electronic devices and systems has historically been addressed at the Printed Circuit Board (PCB) and system level. Today, with the introduction of compact system-on-chip (SOC) technologies, it is increasingly necessary to address EMC issues directly at the package and IC level. As ICs continue to evolve with increasing complexity and performance, the adoption of advanced package technologies becomes essential to accommodate the growing number of functionalities and I/O pins of future IC designs. The continuous transformation has given rise to various IC package types, ranging from Dual In-line Packages (DIPs) to Small-Outline Packages (SOPs), Chip-Scale Packages (CSPs), Ball Grid Arrays (BGAs), and Multi-Chip Packages (MCPs). Packaging has become an integral aspect of IC design, typically with a focus on meeting the performance requirements of high-speed applications while minimizing the impact of parasitic effects. In this context, issues such as signal and power integrity as well as EMC play an increasing role in IC package design. By focusing on optimal arrangement of the power supply, efficient signal and power integrity management, as well as careful material selection, these new packaging technologies pave the way for the development of EMC-compliant ICs.

It seems obvious that EMC performance can be improved by a suitable choice of the IC package. The influence of the IC package on the parasitic inductances e.g. in the IC’s power supplies seems obvious. These inductances strongly depend on the geometry of the power supply loops and thus on package type and especially the position of the power supply pins within the package. Packages that offer a very small loop area of the power supply tend to reduce the ground bounce amplitude and thus the electromagnetic emission of the ICs. The EMC performance of IC packages was investigated in [1]. In this paper the radiated electromagnetic emission of two different types of packages Plastic Ball Grid A‑ray (PBGA) and Super Ball Grid Array (SBGA) were investigated up to 10 GHz. It was shown, that SBGA packages are substantially better regarding the EMC performance and are highly dependent on the used grounding configuration. In [2], the electromagnetic radiation from IC packages and the potential electromagnetic interference (EMI) are investigated by studying the main principles and characteristics of electromagnetic radiation caused by traces and vias in the IC packages. An attempt to suppress EMI by introducing absorbing material into the IC package is presented in [3]. Thereby the IC package was coated with two different arrangements of thin absorbing materials to reduce the radiated electromagnetic emission caused by the switching activity of the IC. A systematic and fundamental investigation and modeling of the EMI behavior based on the contributions of ground lids, vias and traces of the package is presented in [4]. Basic modeling components for the emission generation are presented to help achieve appropriate guidelines for optimal design of EMI reduction of IC packages. In [5], based on studies of smart power SOCs, interactions between on-chip parasitic capacitors and parasitic package elements, as well as the resulting propagation of electromagnetic emission were demonstrated. The various interaction mechanisms such as package-to-substrate, chip-to-package, and chip-partition-to-partition feedthroughs for representative packages and ICs were investigated and quantified in terms of their EMI impact in [6].

In [7] EMI is also seen as a critical issue for the next generation of system-on-package (SOP) integrated high-performance digital, high-frequency and analog ICs. In this paper next to topics such as die-, package-, and substrate-level EMI, electromagnetic modeling and simulation, near field coupling and its related radiated emission of the IC is discussed by emphasizing signal-return path loops and power/ground line currents as EMI sources. Additionally near electric and magnetic field measurements, based on surface scanning techniques for design validation are explained. In [8], it is shown that the surface sensing method can be used for EMI root cause investigations, since it is possible to locate the sources of electromagnetic emissions based on the field distribution of electric and magnetic fields on the surface of an IC. However, measuring near fields on the surface of microchips and IC packages requires special near field probes with high resolution. The design of a fully integrated active magnetic probe is presented for example in [9].

This paper is structured as follows. Section 2 introduces the generation of electromagnetic emissions (EME) of ICs. The device under test (DUT) used for the investigation in this paper to examine the influence of the power supply pinning arrangement on the IC’s conducted electromagnetic emission is described in Sect. 3. Section 4 briefly explains the used test setups for measuring the conducted as well as the near field emission of the IC. In this way, we would like to highlight how the different power supply pinning configurations influence the generated emissions, which are discussed in Sect. 5.

A large part of the electromagnetic emission (EME) of an IC is caused by the switching activities within the IC itself [10]. Especially the square-wave clock signals and the digital signals of the output drivers play a decisive role. In theory, the harmonics of these signals decrease with frequency. However, it also happens that an increase in EME can occur locally at certain frequency points. These local increases are usually caused by resonances occurring due to interactions of the IC, the IC package and the on- and off-chip decoupling capacitors.

The EME emitted by the IC depends strongly on the package, especially on the arrangement as well as the associated length of the various I/O and supply traces. This dependency can mostly be explained in three ways. The supply pins (VDD and GND) together with the pins/balls, the lead frame traces and the bond wires form conductor loops through which mostly large dynamic current peaks flow. These currents are generated by the IC’s internal switching activity and usually show very high di/dt values. If such a dynamic current flows through the conductor loop formed by the power supply arrangement of the IC, magnetic fields may be emitted from these supply loops. Such magnetic fields can be visualized on the surface of the IC package and in the immediate vicinity using near magnetic field sensing techniques e.g. by using a surface scanning system. If these magnetic fields are too large, they can easily couple into conductor loops of adjacent electronic components and cause a potential EMC problem. This issue becomes more and more relevant especially at high integration densities. The larger the loop area, the better the transmitting antenna it forms. It is therefore important to arrange the IC’s power supply in a way such that the supply loop area is as small as possible.

Additionally, the high di/dt causes voltage drops at the parasitic inductances of these supply loops. These voltage drops result in a potential difference of the IC’s internal supply voltages compared to the supplies on the PCB. This potential difference, often referred to as “GND bounce” or “VDD bounce”, occurs with the IC’s operating frequency and is one reason for the IC’s common mode emission [11]. Furthermore, the parasitic inductances of the loops in the IC’s power supply can together with the internal or external decoupling capacitors form resonant LC circuits.

Usually, the decoupling capacitors in conjunction with these parasitic inductances form a series resonant circuit, which has a very low impedance at its series resonance frequency. This helps to allow dynamic switching currents to be shorted directly across the capacitor adjacent to the IC’s power supply pins. Typically, this results in significantly smaller electromagnetic emissions around this series resonant frequency. However, it is also possible for the decoupling capacitor to combine with inductors to form a parallel resonant circuit that has a high impedance resonance. This often leads to a large voltage drop across the impedance, causing increased EME to be observed in the frequency range around the respective parallel resonant frequency.

By using techniques such as decoupling capacitors, ground planes and signal shielding, ICs with advanced package technologies can more easily meet the EMC requirements [12]. The EMC design and implementation of optimized pin configurations, especially the placement of the power supply pins (VDD and GND) within the package layout, is important. As the number of I/O pins increases, a corresponding increase in the number of power supply pins is required to minimize ground bounce interference and electromagnetic emissions. In addition, the positioning and routing of these pins within the package is critical to minimize the generation and propagation of electromagnetic emissions.

The IC used to study the impact of the power supply arrangement on the electromagnetic emission was designed as an EMC test chip with multiple purposes. It allows to investigate the effects of slew rate controlled output drivers or skewing of the output signals switching timings on the EME. Further information on this test chip can be found in [13] and [14]. It was fabricated in a 0.35 µm CMOS technology with a die-size of about 1.5 × 1.5 mm. The die was mounted in a 24-pin ceramic DIP. This IC package is well suited for studying the parasitic effects of different power supply arrangements because it is very large compared to the die, and thus large loop areas are created in the power supply by long bond wires and the lead frame of the package. In principle, all results can be transferred to other package types, but in this case the values of the parasitic inductances have to be adjusted. A picture of the die and the DIP is shown in Fig. 1.

The DUT consists of eight CMOS inputs, which are connected to eight corresponding output drivers, offering a driving strength of 8 mA. The DUT has three VDD and three GND pins, which on chip connect to a common metal structure thus providing multiple power supply connection options. One pair can be used for classic diagonal corner pinning, and the other two pairs can be used for centered pinning on each side of the IC package.

As a fundamental guideline for correctly aligning the power supply of ICs, it’s imperative to minimize the loop areas formed by the power supply e.g. by using the smallest possible package, or reducing the length of the bond wires. Hence, placing the power supply pins in a manner that minimizes parasitic impedances is crucial. Typically, this involves positioning the pins so that the VDD and GND are in close proximity, leading to very small loop areas and therefore small parasitic inductances. This additionally enables the optimum placement of the decoupling capacitors between these pins on the PCB. If several identical VDD and GND pairs are used on opposite sides of the package (as shown in Fig. 2), the magnetic fields generated by the switching currents of the IC tend to cancel each other out and can therefore be significantly reduced.

For the measurements, the inputs of the IC were driven simultaneously with a 1 MHz digital signal. In order to emulate different load conditions (e.g. capacitive ones such as driving CMOS inputs, or resistive ones such as e.g. LED light indicators) the outputs were loaded with an ohmic-capacitive load (10 kOhm and 47 pF). The RC load emulates both scenarios, generates sufficient electromagnetic emission due to a large dynamic switching current to charge and discharge the capacitive load while switching at 1 MHz, and additionally provides a DC current while the output signal is in a high state via the resistive load. The implementation of the corresponding IC configuration is shown in Fig. 3.

The influence of different power supply arrangements on an IC’s EME was investigated by using two different EMC characterization techniques. For the measurement of the conducted emission the 150 Ohm measurement technique as described in the IEC 61967‑4 standard was used at the ICs VDD connection. The near magnetic field at the surface of the IC package and its surroundings was characterized with the help of a surface scanning technique as described in the part 3 of this standard [15].

In this section, the measurement results of the two measurement methods will be shown and compared against each other. The aim is to find out which power supply arrangement produces the lowest electromagnetic emissions and how large the differences are.

Figure 8 shows the results of the conducted emission measurements of all four different IC supply configurations in an emission plot from 150 kHz to 1 GHz. The switching frequency of 1 MHz and all its harmonics are clearly visible up to the high MHz range. The emission spectrum clearly shows the reduction in emissions due to the use of the decoupling capacitor (especially around its series resonance frequency at ~ 20 MHz). As can be seen, the decoupling capacitor helps to reduce the emission generated by the IC up to about 10–30 MHz, where it still shows capacitive behavior below its series resonance frequency. After that, the parasitic inductance (ESL) of the capacitor itself and especially the loop inductance due to its placement on the PCB start to dominate. This makes the decoupling capacitor less and less effective. At such high frequencies, the results are mainly determined by additional resonances of the entire assembly. This can lead to a significant local increase of EME, as can be observed e.g. around 300 MHz. Such effects can be due to parallel resonances formed e.g. by the die substrate’s capacitance to surrounding elements in combination with the parasitic inductances of the bond wires and lead frame of the IC package.

Comparing the result of a corner vs. a center supply arrangement (see Fig. 4 arrangement (a) vs. Figure 4 arrangement (b)), shows similar results in the frequency range up to ~10 MHz. Here the emission spectrum is mainly determined by the value of the decoupling capacitor itself, which in this case remained unchanged. The additional parasitic inductance caused by the corner arrangement has no influence in this frequency range.

However, as can be seen in the higher frequency range there is a significant difference. Here the center power supply arrangement offers lower parasitic inductances and therefore results in lower emissions of the IC. For a better overview of the measurement results and to allow for easier comparison, Fig. 9 only shows the envelopes of the maximum emission spectral lines. The difference can be up to 15 dB at e.g. ~28 MHz and a slight reduction can be seen over a wide frequency range from 10 MHz to 100 MHz. Although the center supply arrangement shows an improvement in this range, it performs worse than the corner supply arrangement in the frequency range around 300 MHz, which is due to resonances caused by the interaction between the PCB and the IC.

For this test IC the power supply of the center right and center left arrangement were designed in a very symmetrical way, therefore the emission of the two center configurations are nearly identical. By using both center arrangements at the same time (arrangement (c) in Fig. 4) the emission can be reduced even further. Comparing the corresponding envelope emission plots in Fig. 9 shows a reduction of approximately 10 dB to 15 dB over the whole frequency range. This is to be expected, as the two paralleled supply connections approximately half the package induced parasitic loop inductance. Additionally, the paralleled decoupling capacitors further lower the emission in the low-frequency range, as the total capacitance doubles. In the higher frequency range, they reduce the emission as their total parasitic inductance halves due to their parallel connection.

The lowest emission can be observed when all power supply configurations are combined. In this case three decoupling capacitors act together, providing maximum capacitance as well as minimum parasitic inductance in the power supply. This results in a significant decrease in conducted electromagnetic emissions over the entire frequency range.

Figure 10a shows the magnetic near fields at the surface of the IC package and in the immediate vicinity of a corner supply arrangement with the VDD supply pin in the top right corner and the corresponding GND pin in the bottom left corner. As expected, the large supply loop results in a large area being subjected to increased magnetic near field emissions. Figure 10b shows the magnetic near field of the dual sided center arrangement. The results confirm the hypothesis of lower emissions as they show a significant reduction in magnetic field spreading and magnitude compared to the corner arrangement. This is most likely due to the smaller loop area, as well as the effect of counteracting field orientations due to the symmetrical design of the power supply connections. On the right hand side of the IC, the magnetic field magnitude is higher than on the left hand side of the IC. This is to be expected because on this side the output drivers of the IC are connected to the ohmic-capacitive loads. Therefore, the magnetic fields caused by the dynamic switching currents flowing out of and into the output pins of the IC also contribute to the near magnetic fields that are measured in this area.

Even though the arrangement with all supplies connected resulted in the lowest overall conducted electromagnetic emission, the results presented in Fig. 10c (center and corner arrangement) again show a wider spread of magnetic fields with higher magnitude compared to the dual-sided center arrangement in Fig. 10b. The magnitude is still lower than with a single corner arrangement (Fig. 10a), however, the supply current now distributes between the corner arrangement and the center arrangement, allowing a portion of the current to generate increased magnetic fields due to the larger loop area of the corner arrangement.

In this work, two different measurement techniques were used to investigate the influence of the power supply arrangement on the electromagnetic emission of an EMC test chip. In particular, the differences in the emission of corner and center pinning of a dual inline package are compared and discussed. The EMC test chip was operated in a way so that all of its 8 outputs are switching simultaneously with a 1 MHz digital output signal. The generated electromagnetic emission (i.e. harmonics of the 1 MHz signal) extends into the hundreds of MHz range, which provided ideal test conditions for such power supply arrangement investigations. For each of the supply arrangements, a 47 nF decoupling capacitor was used between the respective VDD and GND pins. The measurement results obtained by both measurement techniques (the 150 Ohm method for the conducted emission and the surface scan method for the near magnetic field measurement) showed a significant difference in the electromagnetic emission when different supply arrangements are used. The corner pining arrangement showed in both cases the highest emissions compared to each of the different center arrangements. This is mainly due to the increased power supply loop areas leading to higher parasitic inductances and thus increased conducted emissions and higher near magnetic fields at the surface of the IC package. Using a single center pining arrangement the conducted emission was reduction by about 10 dB over a wide frequency range. This can be attributed to the much smaller power supply loop area caused by the closer pin spacing. Since the pins are now next to each other, the decoupling capacitor can also be placed optimally. When a dual sided center arrangement is used, the emission can further be lowered by up to 10 dB in the higher frequency range. In this case, the measurement of the magnetic near field also shows the lowest emission because now the center pinning arrangement provides a symmetrical supply causing a portion of the magnetic near field to cancel each other out. Combining all power supply arrangements (corner and dual sided center) resulted in the lowest overall conducted electromagnetic emission with a reduction of up to 20 dB. However, the surface scan results show that this supply configuration results in increased magnetic near fields at the surface of the IC. To reduce the conducted emissions of an IC, it is advisable to use as many power supply pins as possible. However, if the near magnetic fields in the close proximity of the IC should be reduced it is recommended to use a power supply arrangement, which is as symmetrical as possible. Such an arrangement is particularly important for densely packed electronic systems where near field coupling can be a potential cause of interference. These findings confirm the importance of the power supply planning in the IC package design during the development of EMC-compliant ICs.