Low Power Interconnect Design

Due to the importance of interconnects in current and future ICs, significant research is going on over the past two decades, covering different areas such as parasitic extraction, interconnect models, and interconnect design methodologies. In this chapter, a brief review of the background of on-chip electrical interconnect is provided. In Sect. 1.1, a typical design flow for application-specific integrated circuits (ASICs) is described. Challenges in DSM technologies due to interconnect dominant behavior are discussed. In Sect. 1.2, different design criteria that need to be considered during the interconnect design procedure are described. The impedance characteristics of interconnect are presented in Sect. 1.3; specially, the resistance, capacitance, and inductance. Interconnect characteristics, models, and design methodologies are reviewed in Sects. 1.4, 1.5, and 1.6, respectively. Finally, some conclusions are offered in Sect. 1.7.

The buffer is a single-input device which has a gain of 1. CMOS buffer is formed by cascading two CMOS inverters back to back. Operation of one CMOS inverter is to invert the input signal to the opposite logic level. Thus a cascaded combination of two such circuits will bring back the input signal to the original level. This property of CMOS buffer is extremely helpful in signal restoration in communicating over long wires. Before we discuss CMOS buffer, we’ll have in-depth knowledge of CMOS inverter and then move to buffer [1]. The inverter is truly the nucleus of all digital designs. Once its operation and properties are clearly understood, designing more intricate structures such as NAND gates, adders, multipliers, and microprocessors is greatly simplified. We can generate and analyze the behavior of these complex circuits completely by extrapolating the results obtained for inverters. This analysis of inverters can be extended to explain the behavior of more complex gates such as NAND, NOR, or XOR, which in turn form the building blocks for modules such as multipliers and processors.

Over the past 10 years, the source of the critical signal delays has undergone a major transition. With the scaling of active device feature sizes into the deep sub-micron regime, the on-chip interconnect has become the primary bottleneck in signal flow within high complexity, high speed integrated circuits (ICs).The smaller feature size in DSM technology nodes reduces the delay of the active devices, however, the effect on delay due to the passive interconnects has increased rapidly, as described by the 2005 International Technology Roadmap for Semiconductors (lTRS) [2]. The transition from an IC dominated by gate delays for feature sizes greater than 250 μm to where the interconnects are the primary source of delay is graphically illustrated in Fig. 3.1. As noted in the figure, the disparity between the relative delay of the interconnect and active devices is exacerbated in each successive technology node. The local wire delay decreases with feature size due to a reduction in the distance among the active devices. Special attention must, however, be placed on the global lines, since the overall speed of current ICs is most often limited by the long distance global interconnects.

In the previous chapter we have discussed about the conventional and efficient buffer insertion technique [1, 3]. By the end of that chapter we also discussed that buffer insertion is going to be inefficient for incoming DSM technologies. In this chapter we would discuss another device insertion technique in very large scale integration (VLSI) interconnects. This chapter deals with another device called Schmidt trigger as a repeater element in interconnects. We would discuss the basic Schmidt trigger and its properties, CMOS implementation of Schmidt trigger and its application in interconnects.

In deep sub-micron technology, minimizing the propagation delay and power consumption on buses is the most important design objective in system-on-chip design. In particular, the coupling effects between wires on the bus can cause serious problems such as crosstalk delay, noise and power consumption. One of the fastest growing areas in computing industry is the provision of high throughput low power digital signal processing (DSP) and Communication systems.