Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Published in:
Blockchain-Enabled Electronics Supply Chain Assurance Read chapter Read first chapter

2021 | OriginalPaper | Chapter

5. Machine Learning in Hardware Security

Authors : Shijin Duan, Zhengang Li, Yukui Luo, Mengshu Sun, Wenhao Wang, Xue (Shelley) Lin, Xiaolin Xu

Published in: Emerging Topics in Hardware Security

Publisher: Springer International Publishing

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

The ever-increasing demand for higher computing capabilities constantly pushes the development of the semiconductor industry and is making modern hardware an extremely complicated artifact. However, with the increased complexity of today’s hardware systems, their security is also challenged by various vulnerabilities coming from different perspectives. Hardware-related security, as an emerging research area, has been gaining more attention during the past decades. As a result, more novel attacks and corresponding countermeasures are being proposed almost every day. The complexity of modern hardware systems makes many conventional methodologies reaching the limit of their analytical capabilities, and new powerful methods and tools are in urgent need to study hardware security problems. Thanks to the significant development of machine learning, numerous advanced analytical methodologies and tools become directly available and applicable to hardware security research, which greatly enhances the ability of both hardware designers and attackers. To present readers the important role played by machine learning in today’s hardware security, this chapter presents the application of machine learning in different hardware security areas, such as IP protection, Trojan detection, side-channel analysis/attacks, hardware security primitives, and architectural vulnerabilities, and highlights future research directions.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
previous chapter Security of AI Hardware Systems
next chapter Security Assessment of High-Level Synthesis
Literature
1.
S. Bhunia, M. Tehranipoor, Hardware Security: A Hands-On Learning Approach (Morgan Kaufmann, Burlington, 2018)
2.
M. Brzozowski, V.N. Yarmolik, Obfuscation as intellectual rights protection in VHDL language, in 6th International Conference on Computer Information Systems and Industrial Management Applications (CISIM’07) (IEEE, Piscataway, 2007), pp. 337–340
3.
P. Subramanyan, S. Ray, S. Malik, Evaluating the security of logic encryption algorithms, in 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (IEEE, Piscataway, 2015), pp. 137–143
4.
M. El Massad, S. Garg, M.V. Tripunitara, Integrated circuit (IC) decamouflaging: reverse engineering camouflaged ICs within minutes, in NDSS (2015), pp. 1–14
5.
X. Xu, B. Shakya, M.M. Tehranipoor, D. Forte, Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks, in International Conference on Cryptographic Hardware and Embedded Systems (Springer, Berlin, 2017), pp. 189–210MATH
6.
M. Li, K. Shamsi, T. Meade, Z. Zhao, B. Yu, Y. Jin, D.Z. Pan, Provably secure camouflaging strategy for IC protection. IEEE Trans. Comput. Aided Desig. Integ. Circuits Syst. 38, 1399–1412 (2017)CrossRef
7.
K. Shamsi, M. Li, T. Meade, Z. Zhao, D.Z. Pan, Y. Jin, Appsat: approximately deobfuscating integrated circuits, in 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (IEEE, Piscataway, 2017), pp. 95–100
8.
D.D. Lewis, J. Catlett, Heterogeneous uncertainty sampling for supervised learning, in Machine Learning Proceedings 1994 (Elsevier, Amsterdam, 1994), pp. 148–156
9.
A. Ehrenfeucht, D. Haussler, M. Kearns, L. Valiant, A general lower bound on the number of examples needed for learning. Inf. Comput. 82(3), 247–261 (1989)MathSciNetMATHCrossRef
10.
M. Yasin, B. Mazumdar, O. Sinanoglu, J. Rajendran, Removal attacks on logic locking and camouflaging techniques. IEEE Trans. Emerg. Topics Comput. 8, 517–532 (2017)CrossRef
11.
P. Chakraborty, J. Cruz, S. Bhunia, Sail: machine learning guided structural analysis attack on hardware obfuscation, in 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) (IEEE, Piscataway, 2018), pp. 56–61CrossRef
12.
Y. Xie, A. Srivastava, Anti-sat: mitigating sat attack on logic locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2), 199–207 (2018)CrossRef
13.
M. Yasin, A. Sengupta, M.T. Nabeel, M. Ashraf, J. Rajendran, O. Sinanoglu, Provably-secure logic locking: from theory to practice, in Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (2017), pp. 1601–1618
14.
M. Yasin, B. Mazumdar, J.J.V. Rajendran, O. Sinanoglu, Sarlock: sat attack resistant logic locking, in 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (IEEE, Piscataway, 2016), pp. 236–241
15.
J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, Security analysis of logic obfuscation, in Proceedings of the 49th Annual Design Automation Conference (2012), pp. 83–89
16.
B. Shakya, X. Xu, M. Tehranipoor, D. Forte, Cas-lock: a security-corruptibility trade-off resilient logic locking scheme. IACR Trans. Cryptogr. Hardware Embed. Syst. 2020, 175–202 (2020)
17.
X. Wang, M. Tehranipoor, J. Plusquellic, Detecting malicious inclusions in secure hardware: challenges and solutions, in 2008 IEEE International Workshop on Hardware-Oriented Security and Trust (2008), pp. 15–19
18.
F. Wolff, C. Papachristou, S. Bhunia, R.S. Chakraborty, Towards Trojan-free trusted ICS: problem analysis and detection scheme, in 2008 Design, Automation and Test in Europe (2008), pp. 1362–1365
19.
J. Rajendran, E. Gavas, J. Jimenez, V. Padman, R. Karri, Towards a comprehensive and systematic classification of hardware Trojans, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (2010), pp. 1871–1874
20.
Y. Jin, Y. Makris, Hardware Trojan detection using path delay fingerprint, in 2008 IEEE International Workshop on Hardware-Oriented Security and Trust (2008), pp. 51–57
21.
J. Li, J. Lach, At-speed delay characterization for ic authentication and Trojan horse detection, in 2008 IEEE International Workshop on Hardware-Oriented Security and Trust (2008), pp. 8–14
22.
S. Narasimhan, S. Bhunia, Hardware Trojan detection, in Introduction to Hardware Security and Trust (Springer, Berlin, 2012), pp. 339–364CrossRef
23.
N. Vashistha, M.T. Rahman, H.-T. Shen, D.L. Woodard, N. Asadizanjani, M.M. Tehranipoor, Detecting hardware Trojans inserted by untrusted foundry using physical inspection and advanced image processing. J. Hardw. Syst. Secur. 2, 333–344 (2018)CrossRef
24.
25.
K. Hasegawa, M. Yanagisawa, N. Togawa, Hardware Trojans classification for gate-level netlists using multi-layer neural networks, in 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) (2017), pp. 227–232
26.
T. Iwase, Y. Nozaki, M. Yoshikawa, T. Kumaki, Detection technique for hardware Trojans using machine learning in frequency domain, in 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE) (2015), pp. 185–186
27.
N. Vashistha, Trojan scanner: detecting hardware Trojans with rapid imaging combined with image processing and machine learning (2018)
28.
S. Narasimhan, D. Du, R.S. Chakraborty, S. Paul, F.G. Wolff, C.A. Papachristou, K. Roy, S. Bhunia, Hardware Trojan detection by multiple-parameter side-channel analysis. IEEE Trans. Comput. 62(11), 2183–2195 (2012)MathSciNetMATHCrossRef
29.
D.G. Drmanac, F. Liu, L.-C. Wang, Predicting variability in nanoscale lithography processes, in 2009 46th ACM/IEEE Design Automation Conference (IEEE, Piscataway, 2009), pp. 545–550
30.
A. Vakil, F. Behnia, A. Mirzaeian, H. Homayoun, N. Karimi, A. Sasan, LASCA: learning assisted side channel delay analysis for hardware Trojan detection. e-prints, arXiv:2001.06476 (2020)
31.
G. Hospodar, B. Gierlichs, E. De Mulder, I. Verbauwhede, J. Vandewalle, Machine learning in side-channel analysis: a first study. J. Cryptogr. Eng. 1(4), 293 (2011)
32.
L. Lerman, G. Bontempi, O. Markowitch, Side channel attack: an approach based on machine learning, in Center for Advanced Security Research Darmstadt (2011), pp. 29–41
33.
J. Park, X. Xu, Y. Jin, D. Forte, M. Tehranipoor, Power-based side-channel instruction-level disassembler, in 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2018), pp. 1–6
34.
S. Picek, A. Heuser, A. Jovic, S. Bhasin, F. Regazzoni, The curse of class imbalance and conflicting metrics with machine learning for side-channel evaluations. IACR Trans. Crypto. Hardware Embedded Syst. 2019(1), 1–29 (2019)
35.
W. Hua, Z. Zhang, G.E. Suh, Reverse engineering convolutional neural networks through side-channel information leaks, in 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2018), pp. 1–6
36.
S. Chari, J.R. Rao, P. Rohatgi, Template attacks, in International Workshop on Cryptographic Hardware and Embedded Systems (Springer, Berlin, 2002), pp. 13–28MATH
37.
S. Picek, A. Heuser, A. Jovic, S.A. Ludwig, S. Guilley, D. Jakobovic, N. Mentens, Side-channel analysis and machine learning: a practical perspective, in 2017 International Joint Conference on Neural Networks (IJCNN) (IEEE, Piscataway, 2017), pp. 4095–4102
38.
39.
V. Vapnik, The Nature of Statistical Learning Theory (Springer Science & Business Media, Berlin, 2013)MATH
40.
41.
J.J. Rodriguez, L.I. Kuncheva, C.J. Alonso, Rotation forest: a new classifier ensemble method. IEEE Trans. Pattern Anal. Mach. Intell. 28(10), 1619–1630 (2006)CrossRef
42.
S. Picek, A. Heuser, A. Jovic, A. Legay, Climbing down the hierarchy: hierarchical classification for machine learning side-channel attacks, in International Conference on Cryptology in Africa (Springer, Berlin, 2017), pp. 61–78MATH
43.
T. McGrath, I.E. Bagci, Z.M. Wang, U. Roedig, R.J. Young, A puf taxonomy. Appl. Phys. Rev. 6(1), 011303 (2019)
44.
G.E. Suh, S. Devadas, Physical unclonable functions for device authentication and secret key generation, in 2007 44th ACM/IEEE Design Automation Conference (IEEE, Piscataway, 2007), pp. 9–14
45.
S. Morozov, A. Maiti, P. Schaumont, A comparative analysis of delay based PUF implementations on FPGA. IACR Cryptol. ePrint Arch. 2009, 629 (2009)
46.
X. Xu, S. Li, R. Kumar, W. Burleson, When the physical disorder of cmos meets machine learning, in Low Power Semiconductor Devices and Processes for Emerging Applications in Communications, Computing, and Sensing (2018)
47.
U. Rührmair, J. Sölter, F. Sehnke, X. Xu, A. Mahmoud, V. Stoyanova, G. Dror, J. Schmidhuber, W. Burleson, S, Devadas, PUF modeling attacks on simulated and silicon data. IEEE Trans. Inf. Forensics Secur. 8(11), 1876–1891 (2013)CrossRef
48.
Q. Ma, C. Gu, N. Hanley, C. Wang, W. Liu, M. O’Neill, A machine learning attack resistant multi-PUF design on FPGA, in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (IEEE, Piscataway, 2018), pp. 97–104
49.
J. Delvaux, Machine-learning attacks on polypufs, OB-PUFS, RPUFS, LHS-PUFS, and PUF–FSMS. IEEE Trans. Inf. Forensics Secur. 14(8), 2043–2058 (2019)CrossRef
50.
J.A.K. Suykens, J. Vandewalle, Least squares support vector machine classifiers. Neural Proces. Lett. 9(3), 293–300 (1999)CrossRef
51.
L.K. Hansen, P. Salamon, Neural network ensembles. IEEE Trans. Patt. Anal. Mach. Intell. 12(10), 993–1001 (1990)CrossRef
52.
R.E. Wright, Logistic regression, in Reading and Understanding Multivariate Statistics (American Psychological Association, Washington, 1995), pp. 217–244
53.
54.
M. McCloskey, N.J. Cohen, Catastrophic interference in connectionist networks: the sequential learning problem, in Psychology of Learning and Motivation, vol. 24 (Elsevier, Amsterdam, 1989), pp. 109–165
55.
T. Back, Evolutionary Algorithms in Theory and Practice: Evolution Strategies, Evolutionary Programming, Genetic Algorithms (Oxford University Press, Oxford, 1996)MATHCrossRef
56.
G.T. Becker, The gap between promise and reality: On the insecurity of XOR arbiter PUFs, in International Workshop on Cryptographic Hardware and Embedded Systems (Springer, Berlin, 2015), pp. 535–555MATH
57.
X. Xu, U. Rührmair, D.E. Holcomb, W. Burleson, Security evaluation and enhancement of bistable ring PUFs, in International Workshop on Radio Frequency Identification: Security and Privacy Issues (Springer, Berlin, 2015), pp. 3–16
58.
A. Mahmoud, U. Rührmair, M. Majzoobi, F. Koushanfar, Combined modeling and side channel attacks on strong PUFs. IACR Cryptol. ePrint Arch. 2013, 632 (2013)
59.
X. Xu, W. Burleson, Hybrid side-channel/machine-learning attacks on pufs: a new threat? in 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, Piscataway, 2014), pp. 1–6
60.
U. Rührmair, X. Xu, J. Sölter, A. Mahmoud, M. Majzoobi, F. Koushanfar, W. Burleson, Efficient power and timing side channels for physical unclonable functions, in International Workshop on Cryptographic Hardware and Embedded Systems (Springer, Berlin, 2014), pp. 476–492MATH
61.
C.S. Petrie, J.A. Connelly, A noise-based IC random number generator for applications in cryptography. IEEE Trans. Circ. Syst. I Fund. Theory Appl. 47(5), 615–621 (2000)CrossRef
62.
X. Xu, V. Suresh, R. Kumar, W. Burleson, Post-silicon validation and calibration of hardware security primitives, in 2014 IEEE Computer Society Annual Symposium on VLSI (IEEE, Piscataway, 2014), pp. 29–34CrossRef
63.
S. Best, X. Xu, An all-digital true random number generator based on chaotic cellular automata topology, in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2019), pp. 1–8
64.
M. Matsumoto, T. Nishimura, Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator. ACM Trans. Model. Comput. Simul. (TOMACS) 8(1), 3–30 (1998)
65.
66.
M.W. Thomlinson, D.R. Simon, B. Yee, Non-biased pseudo random number generator (1998). US Patent 5778069
67.
J. Kelsey, B. Schneier, D. Wagner, C. Hall, Cryptanalytic attacks on pseudorandom number generators, in International Workshop on Fast Software Encryption (Springer, Berlin, 1998), pp. 168–188MATH
68.
F. Fan, G. Wang, Learning from pseudo-randomness with an artificial neural network–does god play pseudo-dice? IEEE Access 6, 22987–22992 (2018)CrossRef
69.
T. Fischer, Testing cryptographically secure pseudo random number generators with artificial neural networks, in 2018 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications / 12th IEEE International Conference on Big Data Science and Engineering (TrustCom/BigDataSE) (IEEE, Piscataway, 2018), pp. 1214–1223
70.
X. Xu, W. Burleson, D.E. Holcomb, Using statistical models to improve the reliability of delay-based PUFS, in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (IEEE, Piscataway, 2016), pp. 547–552CrossRef
71.
H. Sayadi, H. Farbeh, A.M.H. Monazzah, S.G. Miremadi, A data recomputation approach for reliability improvement of scratchpad memory in embedded systems, in 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (IEEE, Piscataway, 2014), pp. 228–233
72.
N. Patel, A. Sasan, H. Homayoun, Analyzing hardware based malware detectors, in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2017), pp. 1–6
73.
H. Sayadi, N. Patel, S. Manoj P.D., A. Sasan, S. Rafatirad, H. Homayoun, Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification, in 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2018), pp. 1–6
74.
H. Sayadi, H.M. Makrani, O. Randive, S. Manoj P.D., S. Rafatirad, H. Homayoun, Customized machine learning-based hardware-assisted malware detection in embedded devices, in 2018 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications/12th IEEE International Conference on Big Data Science and Engineering (TrustCom/BigDataSE) (IEEE, Piscataway, 2018), pp. 1685–1688
75.
Z. Xu, S. Ray, P. Subramanyan, S. Malik, Malware detection using machine learning based analysis of virtual memory access patterns, in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 (IEEE, Piscataway, 2017), pp. 169–174
76.
G. Jacob, H. Debar, E. Filiol, Behavioral detection of malware: from a survey towards an established taxonomy. J. Comput. Virol. 4(3), 251–266 (2008)CrossRef
77.
F. Xue, Attacking antivirus, in Black Hat Europe Conference (2008)
78.
J. Demme, M. Maycock, J. Schmitz, A. Tang, A. Waksman, S. Sethumadhavan, S. Stolfo, On the feasibility of online malware detection with performance counters. ACM SIGARCH Comput. Archit. News 41(3), 559–570 (2013)CrossRef
79.
M. Ozsoy, C. Donovick, I. Gorelik, N. Abu-Ghazaleh, D. Ponomarev, Malware-aware processors: a framework for efficient online malware detection, in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) (IEEE, Piscataway, 2015), pp. 651–661
80.
N.L. Petroni Jr, T. Fraser, J. Molina, W.A. Arbaugh, Copilot – a coprocessor-based kernel runtime integrity monitor, in USENIX Security Symposium, San Diego (2004), pp. 179–194
81.
H. Sayadi, H.M. Makrani, S.M.P. Dinakarrao, T. Mohsenin, A. Sasan, S. Rafatirad, H. Homayoun, 2smart: a two-stage machine learning-based approach for run-time specialized hardware-assisted malware detection, in 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, Piscataway, 2019), pp. 728–733CrossRef
82.
A. Tang, S. Sethumadhavan, S.J. Stolfo, Unsupervised anomaly-based malware detection using hardware features, in International Workshop on Recent Advances in Intrusion Detection (Springer, Berlin, 2014), pp. 109–129
83.
K.N. Khasawneh, M. Ozsoy, C. Donovick, N. Abu-Ghazaleh, D. Ponomarev, Ensemble learning for low-level hardware-supported malware detection, in International Symposium on Recent Advances in Intrusion Detection (Springer, Berlin, 2015), pp. 3–25
84.
K.-B. Duan, S.S. Keerthi, Which is the best multiclass svm method? An empirical study, in International Workshop on Multiple Classifier Systems (Springer, Berlin, 2005), pp. 278–285
85.
E. Aghaei, G. Serpen, Ensemble classifier for misuse detection using n-gram feature vectors through operating system call traces. Int. J. Hybrid Intell. Syst. 14(3), 141–154 (2017)CrossRef
Metadata
Title
Machine Learning in Hardware Security
Authors
Shijin Duan
Zhengang Li
Yukui Luo
Mengshu Sun
Wenhao Wang
Xue (Shelley) Lin
Xiaolin Xu
Copyright Year
2021
Book
Emerging Topics in Hardware Security

Print ISBN: 978-3-030-64447-5

Electronic ISBN: 978-3-030-64448-2

Copyright Year: 2021

DOI
https://doi.org/10.1007/978-3-030-64448-2_5