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Published in: Journal of Computational Electronics 4/2017

02-09-2017 | S.I. : Computational Electronics of Emerging Memory Elements

Memory selector devices and crossbar array design: a modeling-based assessment

Author: An Chen

Published in: Journal of Computational Electronics | Issue 4/2017

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Abstract

Functional and scalable memory selector devices are essential for high-density memory and storage. This paper reviews the performance requirements and device options of two-terminal memory selectors for crossbar arrays. In a large crossbar array without appropriate selector devices, large number of sneak paths will significantly degrade the reading signal and writing conditions. Asymmetry and nonlinearity in selector device characteristics can both improve crossbar array operation by making sneak paths more resistive. Rectifying diodes, nonlinear devices, and volatile switches can provide basic selector functions; however, they also need to be balanced with memory elements and meet rigorous requirements in large arrays. Modeling plays an important role in the assessment of selector device function and crossbar array performance. This paper will review the selector device and crossbar array modeling approaches and summarize key observations. The design of large crossbar arrays with functional selector devices requires a comprehensive approach that incorporates device characteristics, array parameters, operation conditions, and application specifications.

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Literature
1.
go back to reference Emerging Research Devices, the International Technology Roadmap of Semiconductors (ITRS) (2015) Emerging Research Devices, the International Technology Roadmap of Semiconductors (ITRS) (2015)
2.
go back to reference Chen, A.: A review of emerging non-volatile memory (NVM) technologies and applications. Solid State Electron. 125, 25–28 (2016)CrossRef Chen, A.: A review of emerging non-volatile memory (NVM) technologies and applications. Solid State Electron. 125, 25–28 (2016)CrossRef
3.
go back to reference Haron, N.Z., Hamdioui, S.: Emerging crossbar-based hybrid nanoarchitectures for future computing systems. In: International Conference on Signals, Circuits and Systems (2008) Haron, N.Z., Hamdioui, S.: Emerging crossbar-based hybrid nanoarchitectures for future computing systems. In: International Conference on Signals, Circuits and Systems (2008)
4.
go back to reference Choi, H., Jung, H., Lee, J., Yoon, J., Park, J., Seong, D.J., Lee, W., Hasan, M., Jung, G.Y., Hwang, H.: An electrically modifiable synapse array of resistive switching memory. Nanotech. 20, 345201-1-5 (2009) Choi, H., Jung, H., Lee, J., Yoon, J., Park, J., Seong, D.J., Lee, W., Hasan, M., Jung, G.Y., Hwang, H.: An electrically modifiable synapse array of resistive switching memory. Nanotech. 20, 345201-1-5 (2009)
5.
go back to reference Burr, G.W., Shelby, R.M., di Nolfo, C., Jang, J.W., Shenoy, R.S., Narayanan, P., Virwani, K., Giacometti, E.U., Kurdi, B., Hwang, H.: Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element. In: IEDM Technical Digest, pp. 697–700, Dec 2014 Burr, G.W., Shelby, R.M., di Nolfo, C., Jang, J.W., Shenoy, R.S., Narayanan, P., Virwani, K., Giacometti, E.U., Kurdi, B., Hwang, H.: Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element. In: IEDM Technical Digest, pp. 697–700, Dec 2014
6.
go back to reference Chen, A.: Nonlinearity and asymmetry for device selection in cross-bar memory arrays. IEEE Trans. Electron. Dev. 62, 2857–2864 (2015)CrossRef Chen, A.: Nonlinearity and asymmetry for device selection in cross-bar memory arrays. IEEE Trans. Electron. Dev. 62, 2857–2864 (2015)CrossRef
7.
go back to reference Linn, E., Rosezin, R., Kügeler, C., Waser, R.: Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9, 403–406 (2010)CrossRef Linn, E., Rosezin, R., Kügeler, C., Waser, R.: Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9, 403–406 (2010)CrossRef
8.
go back to reference Rosezin, R., Linn, E., Nielen, L., Kügeler, C., Bruchhaus, R., Waser, R.: Integrated complementary resistive switches for passive high-density nanocrossbar arrays. IEEE Electron. Dev. Lett. 32, 191–193 (2011)CrossRef Rosezin, R., Linn, E., Nielen, L., Kügeler, C., Bruchhaus, R., Waser, R.: Integrated complementary resistive switches for passive high-density nanocrossbar arrays. IEEE Electron. Dev. Lett. 32, 191–193 (2011)CrossRef
9.
go back to reference Tappertzhofen, S., Linn, E., Nielen, L., Rosezin, R., Lentz, F., Bruchhaus, R., Valov, I., Bottger, U., Waser, R.: Capacity based nondestructive readout for complementary resistive switches. Nanotech. 22, 395203-1-7 (2011)CrossRef Tappertzhofen, S., Linn, E., Nielen, L., Rosezin, R., Lentz, F., Bruchhaus, R., Valov, I., Bottger, U., Waser, R.: Capacity based nondestructive readout for complementary resistive switches. Nanotech. 22, 395203-1-7 (2011)CrossRef
10.
go back to reference Chen, A., Haddad, S., Wu, Y.C., Fang, T.N., Lan, Z., Avanzino, S., Pangrle, S., Buynoski, M., Rathor, M., Cai, W., Tripsas, N., Bill, C., Van Buskirk, M., Taguchi, M.: Non-volatile resistive switching for advanced memory applications. In: IEDM Technical Digest, pp. 746–749, Dec 2005 Chen, A., Haddad, S., Wu, Y.C., Fang, T.N., Lan, Z., Avanzino, S., Pangrle, S., Buynoski, M., Rathor, M., Cai, W., Tripsas, N., Bill, C., Van Buskirk, M., Taguchi, M.: Non-volatile resistive switching for advanced memory applications. In: IEDM Technical Digest, pp. 746–749, Dec 2005
11.
go back to reference Lian, W., Lv, H., Liu, Q., Long, S., Wang, W., Wang, Y., Li, Y., Zhang, S., Dai, Y., Chen, J., Liu, M.: Improved resistive switching uniformity in \({\text{ Cu }}/{\text{ HfO }}_{2}/{\text{ Pt }}\) devices by using current sweeping mode. IEEE Electron. Dev. Lett. 32, 1053–3055 (2011)CrossRef Lian, W., Lv, H., Liu, Q., Long, S., Wang, W., Wang, Y., Li, Y., Zhang, S., Dai, Y., Chen, J., Liu, M.: Improved resistive switching uniformity in \({\text{ Cu }}/{\text{ HfO }}_{2}/{\text{ Pt }}\) devices by using current sweeping mode. IEEE Electron. Dev. Lett. 32, 1053–3055 (2011)CrossRef
12.
go back to reference Burr, G.W., Shenoy, R.S., Virwani, K., Narayanan, P., Padilla, A., Kurdi, B.: Access devices for 3D crosspoint memory. J. Vac. Sci. Technol. 32, 040802-1-23 (2014) Burr, G.W., Shenoy, R.S., Virwani, K., Narayanan, P., Padilla, A., Kurdi, B.: Access devices for 3D crosspoint memory. J. Vac. Sci. Technol. 32, 040802-1-23 (2014)
13.
go back to reference Oh, J.H., et al.: Full integration of highly manufacturable 512 Mb PRAM based on 90nm technology. In: IEDM Technical Digest, pp. 515–518, Dec 2006 Oh, J.H., et al.: Full integration of highly manufacturable 512 Mb PRAM based on 90nm technology. In: IEDM Technical Digest, pp. 515–518, Dec 2006
14.
go back to reference Lee, K.J., Cho, B.H., Cho, W.Y., Kang, S., Choi, B.G., Oh, H.R., Lee, C.S., Kim, H.J., Park, J.M., Wang, Q., Park, M.H., Ro, Y.H., Choi, J.Y., Kim, K.S., Kim, Y.R., Shin, I.C., Lim, K.W., Cho, H.K., Choi, C.H., Chung, W.R., Kim, D.E., Yu, K.S., Jeong, G.T., Jeong, H.S., Kwak, C.K., Kim, C.H., Kim, K.: A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput. In: ISSCC 26.1, Feb 2007 Lee, K.J., Cho, B.H., Cho, W.Y., Kang, S., Choi, B.G., Oh, H.R., Lee, C.S., Kim, H.J., Park, J.M., Wang, Q., Park, M.H., Ro, Y.H., Choi, J.Y., Kim, K.S., Kim, Y.R., Shin, I.C., Lim, K.W., Cho, H.K., Choi, C.H., Chung, W.R., Kim, D.E., Yu, K.S., Jeong, G.T., Jeong, H.S., Kwak, C.K., Kim, C.H., Kim, K.: A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput. In: ISSCC 26.1, Feb 2007
15.
go back to reference Toda, H.: Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array. Patent US7606059 (2009) Toda, H.: Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array. Patent US7606059 (2009)
16.
go back to reference Woerlee, P.H., Widdershoven, F.P., van Acht, V.M.G., Ikkink, T.J., Lambert, N., Marsman, A.W.: Electrical device having a programmable resistor connected in series to a punch-through diode and method of manufacturing therefor. Patent WO 2005124787, A2 (2005) Woerlee, P.H., Widdershoven, F.P., van Acht, V.M.G., Ikkink, T.J., Lambert, N., Marsman, A.W.: Electrical device having a programmable resistor connected in series to a punch-through diode and method of manufacturing therefor. Patent WO 2005124787, A2 (2005)
17.
go back to reference Shima, H., Zhong, N., Akinaga, H.: Switchable rectifier built with \({\text{ Pt }}/{\text{ TiO }}_{{x}}/{\text{ Pt }}\) trilayer. Appl. Phys. Lett. 94, 082905-1-3 (2009) Shima, H., Zhong, N., Akinaga, H.: Switchable rectifier built with \({\text{ Pt }}/{\text{ TiO }}_{{x}}/{\text{ Pt }}\) trilayer. Appl. Phys. Lett. 94, 082905-1-3 (2009)
18.
go back to reference Huang, J.J., Kuo, C.W., Chang, W.C., Hou, T.H.: Transition of stable rectification to resistive-switching in \({\text{ Ti }}/{\text{ TiO }}_{2}/\text{ Pt }\) oxide diode. Appl. Phys. Lett. 96(26), 262901-1-3 (2010) Huang, J.J., Kuo, C.W., Chang, W.C., Hou, T.H.: Transition of stable rectification to resistive-switching in \({\text{ Ti }}/{\text{ TiO }}_{2}/\text{ Pt }\) oxide diode. Appl. Phys. Lett. 96(26), 262901-1-3 (2010)
19.
go back to reference Kim, K.H., Lee, S.R., Ahnb, S.E., Lee, M.J., Kang, B.S.: Fabication of one-diode-one-resistor memory cell structure of Pt/CuO/Pt/TiN/Pt/CuO/InZnO\(x\)/Pt and the effect of TiN layer on the improved resistance switching characteristics. Thin Solid Films 520, 2272–2277 (2012)CrossRef Kim, K.H., Lee, S.R., Ahnb, S.E., Lee, M.J., Kang, B.S.: Fabication of one-diode-one-resistor memory cell structure of Pt/CuO/Pt/TiN/Pt/CuO/InZnO\(x\)/Pt and the effect of TiN layer on the improved resistance switching characteristics. Thin Solid Films 520, 2272–2277 (2012)CrossRef
20.
go back to reference Sasago, Y., et al.: Cross-point phase change memory with \(\text{4F }^{2}\) cell size driven by low-contact-resistivity poly-Si diode. In: Symposium on VLSI Technology Digest, pp. 24–25, Jun 2009 Sasago, Y., et al.: Cross-point phase change memory with \(\text{4F }^{2}\) cell size driven by low-contact-resistivity poly-Si diode. In: Symposium on VLSI Technology Digest, pp. 24–25, Jun 2009
21.
go back to reference Huby, N., et al.: New selector based on zinc oxide grown by low temperature atomic layer deposition for vertically stacked non-volatile memory devices. Microelectron. Eng. 85(12), 2442–2444 (2008)CrossRef Huby, N., et al.: New selector based on zinc oxide grown by low temperature atomic layer deposition for vertically stacked non-volatile memory devices. Microelectron. Eng. 85(12), 2442–2444 (2008)CrossRef
22.
go back to reference Cho, B., et al.: Rewritable switching of one diode-one resistor nonvolatile organic memory devices. Adv. Mater. 22(11), 1228–1232 (2010)CrossRef Cho, B., et al.: Rewritable switching of one diode-one resistor nonvolatile organic memory devices. Adv. Mater. 22(11), 1228–1232 (2010)CrossRef
23.
go back to reference Shin, Y.C., et al.: \((\text{ In },\text{ Sn })_{2} \text{ O }_{3}/ \text{ TiO }_{2}/\text{ Pt }\) Schottky-type diode switch for the \(\text{ TiO }_{2}\) resistive switching memory array. Appl. Phys. Lett. 92(16), 162904-1-3 (2008)CrossRef Shin, Y.C., et al.: \((\text{ In },\text{ Sn })_{2} \text{ O }_{3}/ \text{ TiO }_{2}/\text{ Pt }\) Schottky-type diode switch for the \(\text{ TiO }_{2}\) resistive switching memory array. Appl. Phys. Lett. 92(16), 162904-1-3 (2008)CrossRef
24.
go back to reference Kim, G.H., et al.: Schottky diode with excellent performance for large integration density of crossbar resistive memory. Appl. Phys. Lett. 100(21), 213508-1-3 (2012) Kim, G.H., et al.: Schottky diode with excellent performance for large integration density of crossbar resistive memory. Appl. Phys. Lett. 100(21), 213508-1-3 (2012)
25.
go back to reference Liu, Z.J., Gan, J.Y., Yew, T.R.: ZnO-based one diode-one resistor device structure for crossbar memory applications. Appl. Phys. Lett. 100, 153503-1-3 (2012) Liu, Z.J., Gan, J.Y., Yew, T.R.: ZnO-based one diode-one resistor device structure for crossbar memory applications. Appl. Phys. Lett. 100, 153503-1-3 (2012)
26.
go back to reference Lee, M.J., Park, Y., Kang, B.S., Ahn, S.E., Lee, C., Kim, K., Xianyu, W., Stefanovich, G., Lee, J.H., Chung, S.J., Kim, Y.H., Lee, C.S., Park, J.B., Yoo, I.K.: 2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications. In: IEDM Technical Digest, Dec (2008) Lee, M.J., Park, Y., Kang, B.S., Ahn, S.E., Lee, C., Kim, K., Xianyu, W., Stefanovich, G., Lee, J.H., Chung, S.J., Kim, Y.H., Lee, C.S., Park, J.B., Yoo, I.K.: 2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications. In: IEDM Technical Digest, Dec (2008)
27.
go back to reference Lee, M.J., et al.: A low-temperature-grown oxide diode as a new switch element for high-density, nonvolatile memories. Adv. Mater. 19(1), 73–76 (2007)MathSciNetCrossRef Lee, M.J., et al.: A low-temperature-grown oxide diode as a new switch element for high-density, nonvolatile memories. Adv. Mater. 19(1), 73–76 (2007)MathSciNetCrossRef
28.
go back to reference Seo, J.W., Baik, S.J., Kang, S.J., Hong, Y.H., Yang, J.H., Lim, K.S.: A ZnO cross-bar array resistive random access memory stacked with heterostructure diodes for eliminating the sneak current effect. Appl. Phys. Lett. 98, 233505-1-3 (2011) Seo, J.W., Baik, S.J., Kang, S.J., Hong, Y.H., Yang, J.H., Lim, K.S.: A ZnO cross-bar array resistive random access memory stacked with heterostructure diodes for eliminating the sneak current effect. Appl. Phys. Lett. 98, 233505-1-3 (2011)
29.
go back to reference Chen, A.: Comprehensive methodology for the design and assessment of crossbar memory array with nonlinear and asymmetric selector devices. In: IEDM Technical Digest, pp. 746–749, Dec 2013 Chen, A.: Comprehensive methodology for the design and assessment of crossbar memory array with nonlinear and asymmetric selector devices. In: IEDM Technical Digest, pp. 746–749, Dec 2013
30.
go back to reference Smit, G.D.J., Rogge, S., Klapwijk, T.M.: Scaling of nano-Schottky-diodes. Appl. Phys. Lett. 81, 3852–3854 (2002)CrossRef Smit, G.D.J., Rogge, S., Klapwijk, T.M.: Scaling of nano-Schottky-diodes. Appl. Phys. Lett. 81, 3852–3854 (2002)CrossRef
31.
go back to reference Gopalakrishnan, K., Shenoy, R.S., Rettner, C.T., Virwani, K., Bethune, D.S., Shelby, R.M., Burr, G.W., Kellock, A., King, R.S., Nguyen, K., Bowers, A.N., Jurich, M., Jackson, B., Friz, A.M., Topuria, T., Rice, P.M., Kurdi, B.N.: Highly scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays. In: Symposium on VLSI Technology, pp. 205–206, Jun 2010 Gopalakrishnan, K., Shenoy, R.S., Rettner, C.T., Virwani, K., Bethune, D.S., Shelby, R.M., Burr, G.W., Kellock, A., King, R.S., Nguyen, K., Bowers, A.N., Jurich, M., Jackson, B., Friz, A.M., Topuria, T., Rice, P.M., Kurdi, B.N.: Highly scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays. In: Symposium on VLSI Technology, pp. 205–206, Jun 2010
32.
go back to reference Shenoy, R.S., Gopalakrishnan, K., Jackson, B., Virwani, K., Burr, G.W., Rettner, C.T., Padilla, A., Bethune, D.S., Shelby, R.M., Kellock, A., Breitwisch, M., Joseph, E.A., Dasaka, R., King, R.S., Nguyen, K., Bowers, A.N., Jurich, M., Friz, A.M., Topuria, T., Rice, P.M., Kurdi, B.N.: Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed-ionic-electronic-conduction (MIEC) materials. In: Symposium on VLSI Technology, pp. 94–95, Jun 2011 Shenoy, R.S., Gopalakrishnan, K., Jackson, B., Virwani, K., Burr, G.W., Rettner, C.T., Padilla, A., Bethune, D.S., Shelby, R.M., Kellock, A., Breitwisch, M., Joseph, E.A., Dasaka, R., King, R.S., Nguyen, K., Bowers, A.N., Jurich, M., Friz, A.M., Topuria, T., Rice, P.M., Kurdi, B.N.: Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed-ionic-electronic-conduction (MIEC) materials. In: Symposium on VLSI Technology, pp. 94–95, Jun 2011
33.
go back to reference Shin, J., et al.: \(\text{ TiO }_{2}\)-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application. J. Appl. Phys. 109(3), 033712-1-4 (2011)CrossRef Shin, J., et al.: \(\text{ TiO }_{2}\)-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application. J. Appl. Phys. 109(3), 033712-1-4 (2011)CrossRef
34.
go back to reference Lee, W., et al.: Varistor-type bidirectional switch (\({J}_{\text{ MAX }} > 10^{7} \text{ A }/\text{ cm }^{2}\), selectivity \({\sim }{10}^{4}\)) for 3D bipolar resistive memory arrays. In: Symposium VLSI Technology, pp. 37–38, Jun 2012 Lee, W., et al.: Varistor-type bidirectional switch (\({J}_{\text{ MAX }} > 10^{7} \text{ A }/\text{ cm }^{2}\), selectivity \({\sim }{10}^{4}\)) for 3D bipolar resistive memory arrays. In: Symposium VLSI Technology, pp. 37–38, Jun 2012
35.
go back to reference Govoreanu, B., Adelmann, C., Redolfi, A., Zhang, L., Clima, S., Jurczak, M.: High-performance metal-insulator-metal tunnel diode selectors. IEEE Electron. Dev. Lett. 35(1), 63–65 (2014)CrossRef Govoreanu, B., Adelmann, C., Redolfi, A., Zhang, L., Clima, S., Jurczak, M.: High-performance metal-insulator-metal tunnel diode selectors. IEEE Electron. Dev. Lett. 35(1), 63–65 (2014)CrossRef
36.
go back to reference Zhang, L., Govoreanu, B., Redolfi, A., Crotti, D., Hody, H., Paraschiv, V., Cosemans, S., Adelmann, C., Witters, T., Clima, S., Chen, Y.Y., Hendrickx, P., Wouters, D.J., Groeseneken, G., Jurczak, M.: Ultrathin metal/amorphous-silicon/metal diode for bipolar RRAM selector applications. In: IEDM Technical Digest, pp. 164–167, Dec 2014 Zhang, L., Govoreanu, B., Redolfi, A., Crotti, D., Hody, H., Paraschiv, V., Cosemans, S., Adelmann, C., Witters, T., Clima, S., Chen, Y.Y., Hendrickx, P., Wouters, D.J., Groeseneken, G., Jurczak, M.: Ultrathin metal/amorphous-silicon/metal diode for bipolar RRAM selector applications. In: IEDM Technical Digest, pp. 164–167, Dec 2014
37.
go back to reference Virwani, K., et al.: Sub-30nm scaling and high-speed operation of fully-confined access-devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials. In: IEDM Technical Digest, pp. 36–39, Dec 2012 Virwani, K., et al.: Sub-30nm scaling and high-speed operation of fully-confined access-devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials. In: IEDM Technical Digest, pp. 36–39, Dec 2012
38.
go back to reference Li, K.S., Lee, M.T., Chen, M.C., Hsu, C.L., Lu, J.M., Lin, C.H., Chen, C.C., Wu, B.W., Hou, Y.F., Lin, C.Y., Chen, Y.J., Lai, T.Y., Li, M.Y., Yang, I., Wu, C.S., Yang, F.L., Yeh, W.K.: Study of sub-5nm RRAM, tunneling selector and selector less device. In: IEEE International Symposium on Circuits and Systems, May 2015 Li, K.S., Lee, M.T., Chen, M.C., Hsu, C.L., Lu, J.M., Lin, C.H., Chen, C.C., Wu, B.W., Hou, Y.F., Lin, C.Y., Chen, Y.J., Lai, T.Y., Li, M.Y., Yang, I., Wu, C.S., Yang, F.L., Yeh, W.K.: Study of sub-5nm RRAM, tunneling selector and selector less device. In: IEEE International Symposium on Circuits and Systems, May 2015
39.
go back to reference Woo, J., et al.: Multi-layer tunnel barrier (\({\text{ Ta }}_{2}{\text{ O }}_{5}/{\text{ TaO }}_{{x}}/{\text{ TiO }}_{2}\)) engineering for bipolar RRAM selector applications. In: VLSI Technology, Symposium, pp. 168–169, Jun 2013 Woo, J., et al.: Multi-layer tunnel barrier (\({\text{ Ta }}_{2}{\text{ O }}_{5}/{\text{ TaO }}_{{x}}/{\text{ TiO }}_{2}\)) engineering for bipolar RRAM selector applications. In: VLSI Technology, Symposium, pp. 168–169, Jun 2013
40.
go back to reference Kawarara, A., Azuma, R., Ikeda, Y., Kawai, K., Katoh, Y., Tanabe, K., Nakamura, T., Sumimoto, Y., Yamada, N., Nakai, N., Sakamoto, S., Hayakawa, Y., Tsuji, K., Yoneda, S., Himeno, A., Origasa, K., Shimakawa, K., Takagi, T., Mikawa, T., Aono, K.: An 8 Mb multi-layered cross-point ReRAM macro with 443 MB/s write throughput. In: ISSCC, 25.6, Feb 2012 Kawarara, A., Azuma, R., Ikeda, Y., Kawai, K., Katoh, Y., Tanabe, K., Nakamura, T., Sumimoto, Y., Yamada, N., Nakai, N., Sakamoto, S., Hayakawa, Y., Tsuji, K., Yoneda, S., Himeno, A., Origasa, K., Shimakawa, K., Takagi, T., Mikawa, T., Aono, K.: An 8 Mb multi-layered cross-point ReRAM macro with 443 MB/s write throughput. In: ISSCC, 25.6, Feb 2012
41.
go back to reference Chevallier, C.J., Siau, C.H., Lim, S.F., Namala, S.R., Matsuoka, M., Bateman, B.L., Rinerson, D.: A \({>}{0.13}\,{\upmu }\text{ m }\) 64 Mb multi-layered conductive metal-oxide memory. In: ISSCC, 14.3, Feb 2010 Chevallier, C.J., Siau, C.H., Lim, S.F., Namala, S.R., Matsuoka, M., Bateman, B.L., Rinerson, D.: A \({>}{0.13}\,{\upmu }\text{ m }\) 64 Mb multi-layered conductive metal-oxide memory. In: ISSCC, 14.3, Feb 2010
42.
go back to reference Lee, H.D., Kim, S.G., Cho, K., Hwang, H., Choi, H., Lee, J., Lee, S.H., Lee, H.J., Suh, J., Chung, S.O., Kim, S., Kim, K.S., Nam, W.S., Cheong, J.T., Kim, J.T., Chae, S., Hwang, E.R., Park, S.N., Sohn, Y.S., Lee, C.G., Shin, H.S., Lee, K.J., Hong, K., Jeong, H.G., Rho, K.M., Kim, Y.K., Chung, S., Nickel, J., Yang, J.J., Cho, H.S., Perner, F., Williams, R.S., Lee, J.H., Park, S.K., Hong, S.J.: Symposium on VLSI Technology, pp. 151–152, Jun 2012 Lee, H.D., Kim, S.G., Cho, K., Hwang, H., Choi, H., Lee, J., Lee, S.H., Lee, H.J., Suh, J., Chung, S.O., Kim, S., Kim, K.S., Nam, W.S., Cheong, J.T., Kim, J.T., Chae, S., Hwang, E.R., Park, S.N., Sohn, Y.S., Lee, C.G., Shin, H.S., Lee, K.J., Hong, K., Jeong, H.G., Rho, K.M., Kim, Y.K., Chung, S., Nickel, J., Yang, J.J., Cho, H.S., Perner, F., Williams, R.S., Lee, J.H., Park, S.K., Hong, S.J.: Symposium on VLSI Technology, pp. 151–152, Jun 2012
43.
go back to reference Lee, M.J., Park, Y., Suh, D.S., Lee, E.H., Seo, S., Kim, D.C., Jung, R., Kang, B.S., Ahn, S.E., Lee, C.B., Seo, D.H., Cha, Y.K., Yoo, I.K., Kim, J.S., Park, B.H.: Two series oxide resistors applicable to high speed and high density nonvolatile memory. Adv. Mater. 19, 3919–3923 (2007)CrossRef Lee, M.J., Park, Y., Suh, D.S., Lee, E.H., Seo, S., Kim, D.C., Jung, R., Kang, B.S., Ahn, S.E., Lee, C.B., Seo, D.H., Cha, Y.K., Yoo, I.K., Kim, J.S., Park, B.H.: Two series oxide resistors applicable to high speed and high density nonvolatile memory. Adv. Mater. 19, 3919–3923 (2007)CrossRef
44.
go back to reference Ha, S.D., Aydogdu, G.H., Ramanathan, S.: Metal-insulator transition and electrically driven memristive characteristics of \({\text{ SmNiO }}_{3}\) thin films. Appl. Phys. Lett. 98, 012105-1-3 (2011) Ha, S.D., Aydogdu, G.H., Ramanathan, S.: Metal-insulator transition and electrically driven memristive characteristics of \({\text{ SmNiO }}_{3}\) thin films. Appl. Phys. Lett. 98, 012105-1-3 (2011)
45.
go back to reference Kau, D., Tang, S., Karpov, I.V., Dodge, R., Klehn, B., Kalb, J.A., Strand, J., Diaz, A., Leung, N., Wu, J., Lee, S., Langtry, T., Chang, K.W., Papagianni, C., Lee, J., Hirst, J., Erra, S., Flores, E., Righos, N., Castro, H., Spadini, G.: A stackable cross point phase change memory. In: IEDM Technical Digest, pp. 617–620, Dec 2009 Kau, D., Tang, S., Karpov, I.V., Dodge, R., Klehn, B., Kalb, J.A., Strand, J., Diaz, A., Leung, N., Wu, J., Lee, S., Langtry, T., Chang, K.W., Papagianni, C., Lee, J., Hirst, J., Erra, S., Flores, E., Righos, N., Castro, H., Spadini, G.: A stackable cross point phase change memory. In: IEDM Technical Digest, pp. 617–620, Dec 2009
47.
go back to reference Kim, S., Liu, X., Park, J., Jung, S., Lee, W., Woo, J., Shin, J., Choi, G., Cho, C., Park, S., Lee, D., Cha, E., Lee, B.H., Lee, H.D., Kim, S.G., Chung, S., Hwang, H.: Ultrathin (\({<}{10}\,{\text{ nm }}\)) \({\text{ Nb }}_{2} {\text{ O }}_{5}/{\text{ NbO }}_{2}\) hybrid memory with both memory and selector characteristics for high density 3D vertically stackable RRAM applications. In: Symposium VLSI Technology, pp. 155–156, Jun 2012 Kim, S., Liu, X., Park, J., Jung, S., Lee, W., Woo, J., Shin, J., Choi, G., Cho, C., Park, S., Lee, D., Cha, E., Lee, B.H., Lee, H.D., Kim, S.G., Chung, S., Hwang, H.: Ultrathin (\({<}{10}\,{\text{ nm }}\)) \({\text{ Nb }}_{2} {\text{ O }}_{5}/{\text{ NbO }}_{2}\) hybrid memory with both memory and selector characteristics for high density 3D vertically stackable RRAM applications. In: Symposium VLSI Technology, pp. 155–156, Jun 2012
48.
go back to reference Lee, M.J., Lee, D., Kim, H., Choi, H.S., Park, J.B., Kim, H.G., Cha, Y.K., Chung, U.I., Yoo, I.K., Kim, K.: Highly-scalable threshold switching select device based on chaclogenide glasses for 3D nanoscaled memory arrays. In: IEDM Technical Digest, pp. 33–35, Dec 2012 Lee, M.J., Lee, D., Kim, H., Choi, H.S., Park, J.B., Kim, H.G., Cha, Y.K., Chung, U.I., Yoo, I.K., Kim, K.: Highly-scalable threshold switching select device based on chaclogenide glasses for 3D nanoscaled memory arrays. In: IEDM Technical Digest, pp. 33–35, Dec 2012
49.
go back to reference Lee, M.-J., Ahn, S.E., Lee, C.B., Kim, C.J., Jeon, S., Chung, U.I., Yoo, I.K., Park, G.S., Han, S., Hwang, I.R., Park, B.H.: A simple device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory. ACS Appl. Mater. Interfaces 3(11), 4475–4479 (2011)CrossRef Lee, M.-J., Ahn, S.E., Lee, C.B., Kim, C.J., Jeon, S., Chung, U.I., Yoo, I.K., Park, G.S., Han, S., Hwang, I.R., Park, B.H.: A simple device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory. ACS Appl. Mater. Interfaces 3(11), 4475–4479 (2011)CrossRef
50.
go back to reference Son, M., Lee, J., Park, J., Shin, J., Choi, G., Jung, S., Lee, W., Kim, S., Park, S., Hwang, H.: Excellent selector characteristics of nanoscale \({\text{ VO }}_{2}\) for high-density bipolar ReRAM applications. IEEE Electron Dev. Lett. 32(11), 1579–1581 (2011)CrossRef Son, M., Lee, J., Park, J., Shin, J., Choi, G., Jung, S., Lee, W., Kim, S., Park, S., Hwang, H.: Excellent selector characteristics of nanoscale \({\text{ VO }}_{2}\) for high-density bipolar ReRAM applications. IEEE Electron Dev. Lett. 32(11), 1579–1581 (2011)CrossRef
51.
go back to reference Jo, S.H., Kumar, T., Narayanan, S., Lu, W., Nazarian, H.: 3D-stackable crossbar resistive memory based on field assisted superlinear threshold (FAST) selector. In: IEDM Technical Digest, pp. 160–163, Dec 2015 Jo, S.H., Kumar, T., Narayanan, S., Lu, W., Nazarian, H.: 3D-stackable crossbar resistive memory based on field assisted superlinear threshold (FAST) selector. In: IEDM Technical Digest, pp. 160–163, Dec 2015
52.
go back to reference Kim, W.G., Lee, H.M., Kim, B.Y., Jung, K.H., Seong, T.G., Kim, S., Jung, H.C., Kim, H.J., Yoo, J.H., Lee, H.D., Kim, S.G., Chung, S., Lee, K.J., Lee, J.H., Kim, H.S., Lee, S.H., Yang, J., Jeon, Y., Williams, R.S.: \({\text{ NbO }}_{2}\)-based low power and cost effective 1S1R switching for high density cross point ReRAM application. In: VLSI Technology, Symposium, pp. 138–139, Jun 2014 Kim, W.G., Lee, H.M., Kim, B.Y., Jung, K.H., Seong, T.G., Kim, S., Jung, H.C., Kim, H.J., Yoo, J.H., Lee, H.D., Kim, S.G., Chung, S., Lee, K.J., Lee, J.H., Kim, H.S., Lee, S.H., Yang, J., Jeon, Y., Williams, R.S.: \({\text{ NbO }}_{2}\)-based low power and cost effective 1S1R switching for high density cross point ReRAM application. In: VLSI Technology, Symposium, pp. 138–139, Jun 2014
53.
go back to reference Ho, C.H., Huang, H.H., Lee, M.T., Hsu, C.L., Lai, T.Y., Chiu, W.C., Lee, M.Y., Chou, T.H., Yang, I., Chen, M.C., Wu, C.S., Chiang, K.H., Yao, Y.D., Hu, C., Yang, F.L.: Threshold vacuum switch (TVS) on 3D-stackable and \({4F}^{2}\) cross-point bipolar and unipolar resistive random access memory. In: IEDM Technical Digest, Dec 2012 Ho, C.H., Huang, H.H., Lee, M.T., Hsu, C.L., Lai, T.Y., Chiu, W.C., Lee, M.Y., Chou, T.H., Yang, I., Chen, M.C., Wu, C.S., Chiang, K.H., Yao, Y.D., Hu, C., Yang, F.L.: Threshold vacuum switch (TVS) on 3D-stackable and \({4F}^{2}\) cross-point bipolar and unipolar resistive random access memory. In: IEDM Technical Digest, Dec 2012
54.
go back to reference Yang, H., Li, M., He, W., Jiang, Y., Lim, K.G., Song, W., Zhuo, Y.Q., Tan, C.C., Chua, E.K., Wang, W., Yang, Y., Ji, R.: Novel selector for high density non-volatile memory with ultra-low holding voltage and \(10^{7}\) on/off ratio. In: Symposium on VLSI Technology, pp. 130–131, Jun 2015 Yang, H., Li, M., He, W., Jiang, Y., Lim, K.G., Song, W., Zhuo, Y.Q., Tan, C.C., Chua, E.K., Wang, W., Yang, Y., Ji, R.: Novel selector for high density non-volatile memory with ultra-low holding voltage and \(10^{7}\) on/off ratio. In: Symposium on VLSI Technology, pp. 130–131, Jun 2015
55.
go back to reference Song, J., Woo, J., Prakash, A., Lee, D., Hwang, H.: Threshold selector with high selectivity and sleep slope for cross-point memory array. IEEE Electron. Dev. Lett. 36, 681–683 (2015)CrossRef Song, J., Woo, J., Prakash, A., Lee, D., Hwang, H.: Threshold selector with high selectivity and sleep slope for cross-point memory array. IEEE Electron. Dev. Lett. 36, 681–683 (2015)CrossRef
56.
go back to reference Luo, Q., Xu, X., Liu, H., Lv, H., Gong, T., Long, S., Liu, Q., Sun, H., Banerjee, W., Li, L., Lu, N., Liu, M.: Cu BEOL compatible selector with high selectivity (\({>}{10}^{7}\)), extremely low off-current (\({\sim }{\text{ pA }}\)) and high endurance (\({>}{10}^{10}\)). In: IEDM Technical Digest, Dec 2015 Luo, Q., Xu, X., Liu, H., Lv, H., Gong, T., Long, S., Liu, Q., Sun, H., Banerjee, W., Li, L., Lu, N., Liu, M.: Cu BEOL compatible selector with high selectivity (\({>}{10}^{7}\)), extremely low off-current (\({\sim }{\text{ pA }}\)) and high endurance (\({>}{10}^{10}\)). In: IEDM Technical Digest, Dec 2015
57.
go back to reference Koo, Y., Baek, K., Hwang, H.: Te-based amorphous binary OTS device with excellent selector characteristics for x-point memory applications. In: Symposium on VLSI Technology, Jun 2016 Koo, Y., Baek, K., Hwang, H.: Te-based amorphous binary OTS device with excellent selector characteristics for x-point memory applications. In: Symposium on VLSI Technology, Jun 2016
58.
go back to reference Li, L., Lu, K., Rajendran, B., Happ, T.D., Lung, H.L., Lam, C., Chan, M.: Driving device comparison for phase-change memory. IEEE Trans. Electron. Dev. 58, 664–671 (2011)CrossRef Li, L., Lu, K., Rajendran, B., Happ, T.D., Lung, H.L., Lam, C., Chan, M.: Driving device comparison for phase-change memory. IEEE Trans. Electron. Dev. 58, 664–671 (2011)CrossRef
59.
go back to reference Zhang, L., Redolfi, A., Adelmann, C., Clima, S., Radu, I.P., Chen, Y.Y., Wouters, D.J., Groeseneken, G., Jurczak, M., Govoreanu, B.: Ultrathin metal/amorphous-silicon/metal diode for bipolar RRAM selector applications. IEEE Electron. Dev. Lett. 35(2), 199–201 (2014)CrossRef Zhang, L., Redolfi, A., Adelmann, C., Clima, S., Radu, I.P., Chen, Y.Y., Wouters, D.J., Groeseneken, G., Jurczak, M., Govoreanu, B.: Ultrathin metal/amorphous-silicon/metal diode for bipolar RRAM selector applications. IEEE Electron. Dev. Lett. 35(2), 199–201 (2014)CrossRef
60.
go back to reference Mandapati, R., Borkar, A.S., Srinivasan, V.S.S., Bafna, P., Karkare, P., Lodha, S., Ganguly, U.: The impact of n-p-n selector-based bipolar RRAM cross-point on array performance. IEEE Trans. Electron. Dev. 60, 3385–3392 (2013)CrossRef Mandapati, R., Borkar, A.S., Srinivasan, V.S.S., Bafna, P., Karkare, P., Lodha, S., Ganguly, U.: The impact of n-p-n selector-based bipolar RRAM cross-point on array performance. IEEE Trans. Electron. Dev. 60, 3385–3392 (2013)CrossRef
61.
go back to reference Deshmukh, S., Mandapati, R., Lashkare, S., Borkar, A., Srinivasan, V.S.S., Lodha, S., Ganguly, U.: Comparison of novel punch-through diode (NPN) selector with MIM selector for bipolar RRAM. In: Non-volatile Memory Technology Symposium(NVMTS), Nov 2012 Deshmukh, S., Mandapati, R., Lashkare, S., Borkar, A., Srinivasan, V.S.S., Lodha, S., Ganguly, U.: Comparison of novel punch-through diode (NPN) selector with MIM selector for bipolar RRAM. In: Non-volatile Memory Technology Symposium(NVMTS), Nov 2012
62.
go back to reference Ielmini, D., Zhang, Y.: Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices. J. Appl. Phys. 102, 054517-1-13 (2007)CrossRef Ielmini, D., Zhang, Y.: Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices. J. Appl. Phys. 102, 054517-1-13 (2007)CrossRef
63.
go back to reference Slesazeck, S., Herzig, M., Mikolajick, T., Ascoli, A., Weiher, M., Tetzlaft, R.: Analysis of Vth variability in NbO\(x\)-based threshold switches. In: Non-volatile Memory Technology Symposium (NVMTS), Dec 2016 Slesazeck, S., Herzig, M., Mikolajick, T., Ascoli, A., Weiher, M., Tetzlaft, R.: Analysis of Vth variability in NbO\(x\)-based threshold switches. In: Non-volatile Memory Technology Symposium (NVMTS), Dec 2016
64.
go back to reference Flocke, A., Noll, T.G.: Fundamental analysis of resistive nano-crossbars for the use in hybrid nano/CMOS-memory. In: 33rd European Solid-State Circuits Conference Munich, pp. 328–331 (2007) Flocke, A., Noll, T.G.: Fundamental analysis of resistive nano-crossbars for the use in hybrid nano/CMOS-memory. In: 33rd European Solid-State Circuits Conference Munich, pp. 328–331 (2007)
65.
go back to reference Flocke, A., Noll, T.G., Kugeler, C., Nauenheim, C., Waser, R.: A fundamental analysis of nano-crossbars with non-linear switching materials and its impact on \({\text{ TiO }}_{2}\) as a resistive layer. In: International Conference on Nanotechnology, pp. 319–322, Aug 2008 Flocke, A., Noll, T.G., Kugeler, C., Nauenheim, C., Waser, R.: A fundamental analysis of nano-crossbars with non-linear switching materials and its impact on \({\text{ TiO }}_{2}\) as a resistive layer. In: International Conference on Nanotechnology, pp. 319–322, Aug 2008
66.
go back to reference Amsinck, C.J., Spigna, N.H.D., Nackashi, D.P., Franzon, P.D.: Scaling constraints in nanoelectronic random-access memories. Nanotech. 16, 2251–2260 (2005)CrossRef Amsinck, C.J., Spigna, N.H.D., Nackashi, D.P., Franzon, P.D.: Scaling constraints in nanoelectronic random-access memories. Nanotech. 16, 2251–2260 (2005)CrossRef
67.
go back to reference Ciprut, A., Friedman, E.G.: Modeling size limitations of resistive crossbar array with cell selectors. IEEE Trans. VLSI Syst. 25, 286–293 (2017)CrossRef Ciprut, A., Friedman, E.G.: Modeling size limitations of resistive crossbar array with cell selectors. IEEE Trans. VLSI Syst. 25, 286–293 (2017)CrossRef
68.
go back to reference Narayanan, P., Burr, G.W., Shenoy, R., Virwani, K., Kurdi, B.: Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays, In: IEDM Technical Digest, Dec 2014 Narayanan, P., Burr, G.W., Shenoy, R., Virwani, K., Kurdi, B.: Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays, In: IEDM Technical Digest, Dec 2014
69.
go back to reference Lee, S., Lee, S., Moon, K., Park, J., Kim, B., Hwang, H.: Comprehensive methodology for ReRAM and selector design guideline of cross-point array. In: IEEE International Memory Workshop (IMW), May 2015 Lee, S., Lee, S., Moon, K., Park, J., Kim, B., Hwang, H.: Comprehensive methodology for ReRAM and selector design guideline of cross-point array. In: IEEE International Memory Workshop (IMW), May 2015
70.
go back to reference Kim, S., Zhou, J., Lu, W.: Crossbar RRAM arrays: selector device requirements during write operation. IEEE Trans. Electron. Dev. 61, 2820–2826 (2014)CrossRef Kim, S., Zhou, J., Lu, W.: Crossbar RRAM arrays: selector device requirements during write operation. IEEE Trans. Electron. Dev. 61, 2820–2826 (2014)CrossRef
71.
go back to reference Zhang, L., Cosemans, S., Wouters, D.J., Groeseneken, G., Jurczak, M., Govoreanu, B.: One-selector one-resistor cross-point array with threshold switching selector. IEEE Trans. Electron. Dev. 62, 3250–3257 (2015)CrossRef Zhang, L., Cosemans, S., Wouters, D.J., Groeseneken, G., Jurczak, M., Govoreanu, B.: One-selector one-resistor cross-point array with threshold switching selector. IEEE Trans. Electron. Dev. 62, 3250–3257 (2015)CrossRef
72.
go back to reference Song, L., Zhang, J., Chen, A., Wu, H., Qian, H., Yu, Z.: An efficient method for evaluating RRAM crossbar array performance. Solid State Electron. 120, 32–40 (2016)CrossRef Song, L., Zhang, J., Chen, A., Wu, H., Qian, H., Yu, Z.: An efficient method for evaluating RRAM crossbar array performance. Solid State Electron. 120, 32–40 (2016)CrossRef
73.
go back to reference Jiang, Z., Huang, P., Zhao, L., Kvatinsky, S., Yu, S., Liu, X., Kang, J., Nishi, Y., Wong, H.S.P.: Performance prediction of large-scale 1S1R resistive memory array using machine learning. In: IEDM Technical Digest, Dec 2015 Jiang, Z., Huang, P., Zhao, L., Kvatinsky, S., Yu, S., Liu, X., Kang, J., Nishi, Y., Wong, H.S.P.: Performance prediction of large-scale 1S1R resistive memory array using machine learning. In: IEDM Technical Digest, Dec 2015
74.
go back to reference Kim, G.H., Kim, K.M., Seok, J.Y., Lee, H.J., Cho, D.Y., Han, J.H., Hwang, C.S.: A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory. Nanotech. 21, 385202-1-7 (2010) Kim, G.H., Kim, K.M., Seok, J.Y., Lee, H.J., Cho, D.Y., Han, J.H., Hwang, C.S.: A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory. Nanotech. 21, 385202-1-7 (2010)
75.
go back to reference Chen, A.: A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics. IEEE Trans. Electron. Dev. 60, 1318–1326 (2013)CrossRef Chen, A.: A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics. IEEE Trans. Electron. Dev. 60, 1318–1326 (2013)CrossRef
76.
go back to reference Sun, W., Lim, H., Shin, H., Lee, W.: Investigation of power dissipation for ReRAM in crossbar array architecture. In: Non-volatile Memory Technology Symposium (NVMTS), Oct 2014 Sun, W., Lim, H., Shin, H., Lee, W.: Investigation of power dissipation for ReRAM in crossbar array architecture. In: Non-volatile Memory Technology Symposium (NVMTS), Oct 2014
77.
go back to reference Choi, S., Sun, W., Lim, H., Shin, H.: An analysis of the read margin and power consumption of crossbar ReRAM arrays. In: IEEE TENCON, Nov 2015 Choi, S., Sun, W., Lim, H., Shin, H.: An analysis of the read margin and power consumption of crossbar ReRAM arrays. In: IEEE TENCON, Nov 2015
78.
go back to reference Chen, F.T., Chen, Y.S., Wu, T.Y., Ku, T.K.: Write scheme allowing reduced LRS nonlinearity requirement in a 3D-RRAM array with selector-less 1TNR architecture. IEEE Electron. Dev. Lett. 35, 223–225 (2014)CrossRef Chen, F.T., Chen, Y.S., Wu, T.Y., Ku, T.K.: Write scheme allowing reduced LRS nonlinearity requirement in a 3D-RRAM array with selector-less 1TNR architecture. IEEE Electron. Dev. Lett. 35, 223–225 (2014)CrossRef
79.
go back to reference Lo, C., Hou, T.H., Chen, M.C., Huang, J.J.: Dependence of read margin on pull-up schemes in high-density one selector-one resistor crossbar array. In: IEEE Transactions on Electron Devices, pp. 420–426, Jan 2013 Lo, C., Hou, T.H., Chen, M.C., Huang, J.J.: Dependence of read margin on pull-up schemes in high-density one selector-one resistor crossbar array. In: IEEE Transactions on Electron Devices, pp. 420–426, Jan 2013
80.
go back to reference Chen, A.: Analysis of partial bias schemes for the writing of crossbar memory arrays. IEEE Trans. Electron. Dev. 62, 2845–2849 (2015)CrossRef Chen, A.: Analysis of partial bias schemes for the writing of crossbar memory arrays. IEEE Trans. Electron. Dev. 62, 2845–2849 (2015)CrossRef
81.
go back to reference Levisse, A., Giraud, B., Noel, J.P., Moreau, M., Portal, J.M.: Sneak path compensation circuit for programming and read operations in RRAM-based crosspoint architectures. In: Non-volatile Memory Technology Symposium (NVMTS), Oct 2015 Levisse, A., Giraud, B., Noel, J.P., Moreau, M., Portal, J.M.: Sneak path compensation circuit for programming and read operations in RRAM-based crosspoint architectures. In: Non-volatile Memory Technology Symposium (NVMTS), Oct 2015
82.
go back to reference Levisse, A., Giraud, B., Noel, J.P., Moreau, M., Portal, J.M.: Capacitor based sneak path compensation circuit for transistor-less ReRAM architectures. In: NANOARCH, Jul 2016 Levisse, A., Giraud, B., Noel, J.P., Moreau, M., Portal, J.M.: Capacitor based sneak path compensation circuit for transistor-less ReRAM architectures. In: NANOARCH, Jul 2016
83.
go back to reference Serb, A., Redman-White, W., Papavassiliou, C., Prodromakis, T.: Practical determination of individual element resistive states in selectorless RRAM arrays. IEEE Trans. Circ. Syst. 63, 827–835 (2016)MathSciNet Serb, A., Redman-White, W., Papavassiliou, C., Prodromakis, T.: Practical determination of individual element resistive states in selectorless RRAM arrays. IEEE Trans. Circ. Syst. 63, 827–835 (2016)MathSciNet
84.
go back to reference Li, Z., Chen, P.-Y., Liu, H., Li, Q., Xu, H., Yu, S.: Quasi-analytical model of 3D vertical RRAM array architecture for Mb-level design. IEEE Trans. Electron. Dev. 64(4), 1568–1574 (2017)CrossRef Li, Z., Chen, P.-Y., Liu, H., Li, Q., Xu, H., Yu, S.: Quasi-analytical model of 3D vertical RRAM array architecture for Mb-level design. IEEE Trans. Electron. Dev. 64(4), 1568–1574 (2017)CrossRef
Metadata
Title
Memory selector devices and crossbar array design: a modeling-based assessment
Author
An Chen
Publication date
02-09-2017
Publisher
Springer US
Published in
Journal of Computational Electronics / Issue 4/2017
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-017-1059-7

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