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Journal of Computational Electronics

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01-12-2013

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

Authors: Punyasloka Bal, M. W. Akram, Partha Mondal, Bahniman Ghosh

Published in: Journal of Computational Electronics | Issue 4/2013

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Abstract

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.

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Bhuwalka, K.K., Schulze, J., Eisele, I.: Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer. Jpn. J. Appl. Phys. 43(7A), 4073–4078 (2004) CrossRef

Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007) CrossRef

Colinge, J.-P., Lee, C.-W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Razavi, P., O’Neill, B., Blake, A., White, M., Kelleher, A.-M., McCarthy, B., Murphy, R.: Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225–229 (2010) CrossRef

Lilienfeld, J.E.: Method and apparatus for controlling electric current. U.S. Patent 1 745 175, Oct. 22, 1925

Gundapaneni, S., Ganguly, S., Kottantharayil, A.: Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling. IEEE Electron Device Lett. 32(3), 261–263 (2011) CrossRef

Kranti, A., Yan, R., Lee, C.-W., Ferain, I., Yu, R., Dehdashti Akhavan, N., Razavi, P., Colinge, J.P.: Junctionless nanowire transistor (JNT): properties and design guidelines. In: Proceedings of the European, Solid-State Device Research Conference (ESSDERC), pp. 357–360 (2010)

Lee, C.W., Ferain, I., Kranti, A., Dehdashti Akhavan, N., Razavi, P., Yan, R., Yu, R., O’Neill, B., Blake, A., White, M., Kelleher, A.M., McCarthy, B., Gheorghe, S., Murphy, R., Colinge, J.P.: Short-channel junctionless nanowire transistors. In: Proc. SSDM, pp. 1044–1045 (2010)

Su, C.-J., Tsai, T.-I., Liou, Y.-L., Lin, Z.-M., Lin, H.-C., Chao, T.-S.: Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett. 32(4), 521–523 (2011) CrossRef

Ghosh, B., Bal, P., Mondal, P.: A junctionless tunnel field effect transistor with low subthreshold slope. J. Comput. Electron. (2013). doi:10.1007/s10825-013-0450-2

10.

Ghosh, B., Akram, M.W.: Junctionless Tunnel Field Effect Transistor. IEEE Electron Device Lett. 35(5) (2013)

11.

Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007) CrossRef

12.

Silvaco, Version 5.15.32.R. (2009). [Online]. Available http://www.silvaco.com

13.

Gundapaneni, S., Bajaj, M., Pandey, R.K., Murali, K.V.R.M., Ganguly, S., Kottantharayil, A.: Effect of band-to-band tunneling on junctionless transistors. IEEE Electron Device Lett. 59(4), 1023–1029 (2012) CrossRef

14.

Lide, D.R.: CRC Handbook on Chemistry and Physics 89th edn. pp. 12–114. Taylor & Francis, London (2008)

15.

Hansch, W., Vogelsang, Th., Kirchner, R., Orlowski, M.: Carrier transport near the Si/SiO₂ interface of a MOSFET. Solid-State Electron. 32(10), 839–849 (1989) CrossRef

16.

Schenk, A.: A model for the field and temperature dependence of SRH lifetimes in silicon. Solid-State Electron. 35(11), 1585–1596 (1992) CrossRef

17.

Vandervorst, W., Brijs, B., Bender, H., Conard, O.T., Petry, J., Richard, O., Van Elshocht, S., Delabie, A., Caymax, M., De Gendt, S.: Physcial characterization of ultrathin high k dielectrics. 2002 MRS Fall Meeting

18.

Seo, J.W., Dieker, Ch., Locquet, J.-P., Mavrou, G., Dimoulas, A.: HfO[sub 2] high-k dielectrics grown on (100) Ge with ultrathin passivation layers: structure and interfacial stability. Appl. Phys. Lett. 87, 221906 (2005). doi:10.1063/1.2137897 CrossRef

19.

Zhu, J., Liu, Z.G.: Structure and dielectric properties of ultra-thin ZrO₂ films for high-k gate dielectric application prepared by pulsed laser deposition. Appl. Phys. A 78(5), 741–744 (2004) CrossRef

20.

Lu, J., Kuo, Y.: Hafnium-doped tantalum oxide high-k dielectrics with sub-2 nm equivalent oxide thickness. Appl. Phys. Lett. 87, 232906 (2005). doi:10.1063/1.2140482 CrossRef

Title: Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)
Authors: Punyasloka Bal
M. W. Akram
Partha Mondal
Bahniman Ghosh
Publication date: 01-12-2013
Publisher: Springer US
Published in: Journal of Computational Electronics / Issue 4/2013
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI: https://doi.org/10.1007/s10825-013-0483-6

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