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2011 | OriginalPaper | Chapter

2. Predictive Technology Model of Conventional CMOS Devices

Author : Yu Cao

Published in: Predictive Technology Model for Robust Nanoelectronic Design

Publisher: Springer US

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Abstract

Bulk CMOS has been the dominant device structure for integrated circuit design during the past decades, because of its excellent scalability. It is expected that such a device type will continue toward the 10 nm regime. To efficiently predict the characteristics of future bulk CMOS, the scaling trends of primary model parameters, such as the threshold voltage and gate dielectric thickness, need to be identified; their association in determining major device characteristics should be well included for accurate model projection. In this chapter, a new generation of Predictive Technology Model (PTM) for conventional CMOS technology is presented to accomplish these goals. Based on a set of essential device models and early stage silicon data, PTM of bulk CMOS is successfully generated down to the 12 nm node. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of Ion is below 10% for both NMOS and PMOS devices. By tuning only ten primary model parameters, PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, PTM correctly captures the sensitivity to process variations.

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Metadata
Title
Predictive Technology Model of Conventional CMOS Devices
Author
Yu Cao
Copyright Year
2011
Publisher
Springer US
Book
Predictive Technology Model for Robust Nanoelectronic Design

Print ISBN: 978-1-4614-0444-6

Electronic ISBN: 978-1-4614-0445-3

Copyright Year: 2011

DOI
https://doi.org/10.1007/978-1-4614-0445-3_2