Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2011 | OriginalPaper | Buchkapitel

2. Predictive Technology Model of Conventional CMOS Devices

verfasst von : Yu Cao

Erschienen in: Predictive Technology Model for Robust Nanoelectronic Design

Verlag: Springer US

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Bulk CMOS has been the dominant device structure for integrated circuit design during the past decades, because of its excellent scalability. It is expected that such a device type will continue toward the 10 nm regime. To efficiently predict the characteristics of future bulk CMOS, the scaling trends of primary model parameters, such as the threshold voltage and gate dielectric thickness, need to be identified; their association in determining major device characteristics should be well included for accurate model projection. In this chapter, a new generation of Predictive Technology Model (PTM) for conventional CMOS technology is presented to accomplish these goals. Based on a set of essential device models and early stage silicon data, PTM of bulk CMOS is successfully generated down to the 12 nm node. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of Ion is below 10% for both NMOS and PMOS devices. By tuning only ten primary model parameters, PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, PTM correctly captures the sensitivity to process variations.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren
Vorheriges Kapitel Introduction
Nächstes Kapitel Predictive Technology Model of Enhanced CMOS Devices
Literatur
1.
2.
“BSIM4 Manual,” University of California, Berkeley, 2005.
3.
Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, “New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation,” CICC, pp. 201–204, 2000.
4.
D. Boning and S. Nassif, “Models of process variations in device and interconnect,” Design of High-Peformance Microprocessor Circuits, Chapter 6, pp. 98–115, IEEE Press, 2000.
5.
M. Miyama, S. Kamohara, M. Hiraki, K. Onozawa, and H. Kunitomo, “Pre-silicon parameter generation methodology using BSIM3 for circuit performance-oriented device optimization,” IEEE Trans. Semiconductor Manufacturing, vol. 14, no. 2, pp. 134–142, May 2001.CrossRef
6.
M. Orshansky, J. An, C. Jiang, B. Liu, C. Riccobene and C. Hu, “Efficient generation of pre-silicon MOS model parameters for early circuit design,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 156–159, Jan. 2001.CrossRef
7.
K. Vasanth, et al., “Predictive BSIM3v3 modeling for the 0.15-0.18 μm CMOS technology node: A process DOE based approach,” IEDM Tech. Dig., pp. 353–356, 1999.
8.
W. Zhao, Y. Cao, “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816–2823, Nov. 2006. (Available at http://​ptm.​asu.​edu)CrossRef
9.
D. Sinitsky, “Physics of future very large-sclae integration (VLSI) MOSFETs,” Ph. D. dissertation, Univ. of California, Berkeley, 1997.
10.
G. M. Yeric, A. F. Tasch, and S. K. Banerjee, “A universal MOSFET mobility degradation model for circuit simulation,” IEEE Trans. Computer-Aided Design, vol. 9, no. 10, pp. 1123–1126, Oct. 1990.CrossRef
11.
Y. M. Agostinelli, G. M. Yeric, and A. F. Tacsh, “Universal MOSFET hold mobility degradation models for circuit simulation,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no.3, pp. 439–445, Mar. 1993.CrossRef
12.
H. Ohta, et al., “High performance 30 nm gate bulk CMOS for 45 nm node with Σ-shaped SiGe-SD,” IEDM Tech. Dig., pp. 6–10, 2005.
13.
K. Goto, et al., “High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs,” IEDM Tech. Dig., pp. 623–626, 2003.
14.
Z. Luo, et al., “High performance and low power transistors integrated in 65 nm bulk CMOS technology,” in IEDM Tech. Dig., 2004, pp. 661–664.
15.
C. C. Wu, et al., “A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications,” IEDM Tech. Dig., pp. 65–68, 2002.
16.
V. Chan, et al., “High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering,” IEDM Tech. Dig., pp. 77–80, 2003.
17.
S.-F. Huang, et al., “High performance 50 nm CMOS devices for microprocessor and embedded processor core applications,” IEDM Tech. Dig., pp. 237–240, 2001.
18.
M. Mehrotra, et al., “60 nm gate length dual-Vt CMOS for high performance applications,” VLSI Tech. Symp., pp. 124–125, 2002.
19.
S. Thompson, et al., “An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V,” IEDM Tech. Dig., pp. 257–260, 2001.
20.
S. Tyagi, et al., “A 130 nm generation logic technology featuring 70 nm transistors dual Vt transistors and 6 layers of Cu interconnects,” IEDM Tech. Dig., pp. 567–570, 2000.
21.
K. K. Young, et al., “A 0.13 μm CMOS technology with 193 nm lithograghy and Cu/low-k for high performance applications,” IEDM Tech. Dig., pp. 563–566, 2000.
22.
M. Hargrove, et al., “High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay,” IEDM Tech. Dig., pp. 627–630, 1998.
23.
L. Su, et al., “A high-performance sub-0.25 μm CMOS technology with multiple threshold and copper interconnects,” VLSI Tech. Symp., pp. 18–19, 1998.
24.
M. Rodder, et al., “A 1.2V, 0.1 μm gate length CMOS technology: design and process issues,” IEDM Tech. Dig., pp. 623–626, 1998.
25.
M. Rodder, et al., “A 0.10 μm gate length CMOS technology with 30Å gate dielectric for 1.0V-1.5V applications,” IEDM Tech. Dig., pp. 223–226, 1997.
26.
M. Rodder, et al., “A sub-0.18 μm gate length CMOS technology for high performance (1.5V) and low power (1.0V),” IEDM Tech. Dig., pp. 563–566, 1996.
27.
M. Bohr, et al., “A high performance 0.25 μm logic technology optimized for 1.8V operation,” IEDM Tech. Dig., pp. 847–850, 1996.
Metadaten
Titel
Predictive Technology Model of Conventional CMOS Devices
verfasst von
Yu Cao
Copyright-Jahr
2011
Verlag
Springer US
Buch
Predictive Technology Model for Robust Nanoelectronic Design

Print ISBN: 978-1-4614-0444-6

Electronic ISBN: 978-1-4614-0445-3

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4614-0445-3_2

Neuer Inhalt

    Bildnachweise