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Erschienen in:
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2011 | OriginalPaper | Buchkapitel

1. Introduction

verfasst von : Yu Cao

Erschienen in: Predictive Technology Model for Robust Nanoelectronic Design

Verlag: Springer US

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Abstract

The scaling of CMOS technology has been the driving force of the semiconductor industry during past five decades, with the minimum feature size expected to reach 10 nm in 10 years [1]. Beyond that benchmark, the present scaling approach may have to take a different route, in order to overcome dramatic barriers in transistor performance degradation, power consumption, process and environmental variations, and reliability issues.

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Nächstes Kapitel Predictive Technology Model of Conventional CMOS Devices
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Metadaten
Titel
Introduction
verfasst von
Yu Cao
Copyright-Jahr
2011
Verlag
Springer US
Buch
Predictive Technology Model for Robust Nanoelectronic Design

Print ISBN: 978-1-4614-0444-6

Electronic ISBN: 978-1-4614-0445-3

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4614-0445-3_1

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