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2011 | OriginalPaper | Chapter

3. Predictive Technology Model of Enhanced CMOS Devices

Author : Yu Cao

Published in: Predictive Technology Model for Robust Nanoelectronic Design

Publisher: Springer US

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Abstract

The scaling of traditional bulk CMOS structure has slowed down in recent years as fundamental physical and process limits are rapidly approached. For instance, short-channel effects, such as drain-induced-barrier-lowering (DIBL) and threshold voltage (Vth) rolloff, severely increase leakage current and degrade the Ion/Ioff ratio (Fig. 2.11) [1]. To overcome these difficulties and continue the path projected by Moore’s law, new materials need to be incorporated into the bulk CMOS structure, including high-permittivity (high-k) gate dielectrics, metal gate electrodes, low-resistance source/drain, and strained Si channel for high mobility [2, 3]. Furthermore, more flexible process choices, such as multiple-Vth, are required in today’s integrated circuit design, in order to satisfy various design needs (e.g., low power vs. high performance). These technology evolutions should be incorporated into PTM to facilitate contemporary design exploration.

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previous chapter Predictive Technology Model of Conventional CMOS Devices
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Metadata
Title
Predictive Technology Model of Enhanced CMOS Devices
Author
Yu Cao
Copyright Year
2011
Publisher
Springer US
Book
Predictive Technology Model for Robust Nanoelectronic Design

Print ISBN: 978-1-4614-0444-6

Electronic ISBN: 978-1-4614-0445-3

Copyright Year: 2011

DOI
https://doi.org/10.1007/978-1-4614-0445-3_3