SiC Material in Si-LDMOS Transistors by Controlling Mismatching at Their Interfaces

In this paper, a new lateral double-diffused metal oxide semiconductor (LDMOS) device is presented by considering the SiC window under the drift region and in the buried oxide. The SiC region with a higher band gap than silicon is useful for increasing the breakdown voltage. However, the mismatch of the SiC and silicon limits the application of this material. In the new SiC window in the LDMOS (SCW-LDMOS) structure, a Si₃N₄ layer is considered between the silicon of the drift region, as well as interface charges at the interface of the SiC/SiO₂. Simulation with the two-dimensional ATLAS simulator shows that the SCW-LDMOS transistor has higher breakdown voltage than the conventional LDMOS structure (C-LDMOS). Moreover, the SiC window creates new peaks in the horizontal electric field and thus reduces the main peaks, which is the main reason for achieving high breakdown voltage. To achieve excellent performance of the new proposed transistor, accurate values of the SiC length, thickness, and doping density are determined. Also, the proper thickness of the Si₃N₄ is chosen in this study.