Top

Journal of Electronic Materials

Published in:

04-12-2023 | Original Research Article

Superior Impact Ionization Rate in Deep Gate LDMOS Devices to Improve the Figure of Merit and Lattice Temperature

Authors: Fateme Rezaei, Ali A. Orouji, Abdollah Abbasi

Published in: Journal of Electronic Materials | Issue 3/2024

Activate our intelligent search to find suitable subject content or patents.

search-config

AI-assisted search

Off

Abstract

This paper introduces a deep gate lateral double-diffused MOSFET (LDMOS) structure. The proposed LDMOS is a superior impact ionization rate (SIIR-LDMOS) transistor. The primary focus of our research was to reduce the impact ionization rate and improve key performance metrics. To address this, we implemented a modified drift region and optimized layout design. One key aspect of the proposed structure is the inclusion of an N-type area in the drift region, specifically aimed at decreasing the impact ionization rates. By reducing these rates, we were able to effectively control the electric field and enhance the figure of merit. The results of our study demonstrate improvements in breakdown voltage, on-state resistance, figure of merit, and maximum lattice temperature by approximately 54.88%, 20.8%, 209.15%, and 10.09%, respectively. Importantly, we observed that the lattice temperature in the SIIR-LDMOS structure was lower than in the conventional LDMOS transistor. This further supports the advantages of our proposed design. The enhanced figure of merit and breakdown voltage strongly position the SIIR-LDMOS as a promising candidate for future power MOSFETs.

previous article A Cu Pillar Bump Bonding Method Using Au-Sn Alloy Cap as the Interconnection Layer

next article Electrical Performance of a Dual-Band Composite Radome

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

inform now

J. Lutz, H. Schlangenotto, U. Scheuermann, and R. De Doncker, Semiconductor power devices. Phys. Char. Reliab. (2011). https://doi.org/10.1007/978-3-642-11125-9.CrossRef

Y. Fan, X. Luo, K. Zhou, Y. Fan, Y. Jiang, Q. Wang, P. Wang, Y. Luo, and B. Zhang, An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement. J. Semicond. 35, 034011 (2014). https://doi.org/10.1088/1674-4926/35/3/034011.CrossRef

T. Erlbacher, Lateral Power Transistors in Integrated Circuits (Berlin: Springer, 2014).CrossRef

Z. Dong, B. Duan, C. Fu, H. Guo, Z. Cao, and Y. Yang, Novel LDMOS optimizing lateral and vertical electric field to improve breakdown voltage by multi-ring technology. IEEE Electron. Device Lett. 39, 1424 (2018). https://doi.org/10.1109/LED.2018.2854417.CrossRef

A. Saadat, M.L. Van De Put, H. Edwards, and W.G. Vandenberghe, Channel length optimization for planar LDMOS field-effect transistors for low-voltage power applications. IEEE J. Electron Devices Soc 8, 1450 (2020). https://doi.org/10.1109/JEDS.2020.3008388.CrossRef

M.K. Anvarifard, An impressive structure containing triple trenches for RF power performance (TT-SOI-MESFET). J. Comput. Electron. 17, 181 (2018). https://doi.org/10.1007/s10825-017-1078-4.CrossRef

M.K. Anvarifard, Symmetrical SOI MESFET with a dual cavity region (DCR-SOI MESFET) to promote high-voltage and radio-frequency performances. Superlattices Microstruct. 98, 203 (2016). https://doi.org/10.1016/j.spmi.2016.09.003.CrossRef

W.J. Kloosterman and M.J. Swanenberg, Modelling of high-voltage SOI-LDMOS transistors including self-heating. Simul. Semicond. Process. Devices (2001). https://doi.org/10.1007/978-3-7091-6244-6_54.CrossRef

J.G. Fiorenza, D.A. Antoniadis, and J.A. Del Alamo, RF power LDMOSFET on SOI. IEEE Electron Device Lett. 22, 147 (2001). https://doi.org/10.1109/55.910622.CrossRefADS

10.

X. Cheng, Z. Song, Y. Dong, Y. Yu, and D. Shen, Patterned silicon-on-insulator technology for RF Power LDMOSFET. Microelectron. Eng. 81, 87 (2005). https://doi.org/10.1016/j.mee.2005.05.001.CrossRef

11.

A. Gavoshani, and A.A. Orouji, A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature. J. Comput. Electron. 20, 1129 (2021). https://doi.org/10.1007/s10825-021-01724-5.CrossRef

12.

A. Gavoshani, A.A. Orouji, and A. Abbasi, A novel deep gate LDMOS structure using double p-trench to improve the breakdown voltage and the on-state resistance. Silicon 14, 585 (2022). https://doi.org/10.1007/s12633-020-00857-9.CrossRef

13.

S. Hu, Y. Chen, J. Jin, J. Zhou, F. Zhou, Z. Chen, Y. Huang, J. Luo, and J. Wang, A low specific on-resistance power trench MOSFET with a buried-interface-drain. Superlattices Microstruct. 85, 751 (2015). https://doi.org/10.1016/j.spmi.2015.05.030.CrossRef

14.

N. Othman, M.K. Md Arshad, S.N. Sabki, and U. Hashim, Ultra-thin body and buried oxide (UTBB) SOI MOSFETs on suppression of short-channel effects (SCEs): a review. Adv. Mater. Res 1109, 257 (2015). https://doi.org/10.4028/www.scientific.net/amr.1109.257.CrossRef

15.

A. Pak and A.A. Orouji, Numerical simulation of lateral diffused metal oxide semiconductor field effect transistors: a novel technique for electric field control to improve breakdown voltage. Mater. Sci. Semicond. Process. 34, 36 (2015). https://doi.org/10.1016/j.mssp.2015.02.027.CrossRef

16.

H.A. Moghadam, A.A. Orouji, and S.E. Jamali Mahabadi, Employing reduced surface field technique by a P-type region in 4H-SiC metal semiconductor field effect transistors for increasing breakdown voltage. Int. J. Numer. Model. Electron. Networks Devices Fields 26, 181 (2013). https://doi.org/10.1002/jnm.1836.CrossRef

17.

S. Xu, K.P. Gan, G.S. Samudra, Y.C. Liang, and J.K.O. Sin, 120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit. IEEE Trans. Electron Devices 47, 2032 (2000). https://doi.org/10.1109/16.870584.CrossRef

18.

M. Mehrad, M. Zareiee, and A.A. Orouji, Controlled kink effect in a novel high-voltage LDMOS transistor by creating local minimum in energy band diagram. IEEE Trans. Electron Devices 64, 4107 (2017). https://doi.org/10.1109/TED.2017.2737531.CrossRef

19.

Silvaco Inc., ATLAS user’s manual: device simulation software. Silvaco (2016), www.silvaco.com.

20.

A. Pak and A.A. Orouji, A novel technique at LDMOSs to improve the figure of merit. Superlattices Microstruct. 93, 94 (2016). https://doi.org/10.1016/j.spmi.2016.02.031.CrossRef

21.

M.K. Anvarifard, A nanoscale-modified junctionless with considerable progress on the electrical and thermal issue. Int. J. Numer. Model Electron. Networks Devices Fields 32, 2537 (2019). https://doi.org/10.1002/jnm.2537.CrossRef

22.

P. Shen, Y. Wang, X.J. Li, J. Qun Yang, and L. Zheng, Simulation study on single-event burnout reliability of 4H-SiC trench gate MOSFET with combined P-buried layer. Microelectron. Reliab 142, 114931 (2023). https://doi.org/10.1016/j.microrel.2023.114931.CrossRef

23.

S. Chahar, G.M. Rather, and N.U.D. Hakim, The effect of shallow trench isolation and sinker on the performance of dual-gate LDMOS device. IEEE Trans. Electron Devices (2019). https://doi.org/10.1109/TED.2018.2881918.CrossRef

24.

M. Zareiee, H. Salami, Inserting PN junction in a power device for achieving improved figure of merit, in 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018, (2018), doi: https://doi.org/10.1109/ULIS.2018.8354777.

Title: Superior Impact Ionization Rate in Deep Gate LDMOS Devices to Improve the Figure of Merit and Lattice Temperature
Authors: Fateme Rezaei
Ali A. Orouji
Abdollah Abbasi
Publication date: 04-12-2023
Publisher: Springer US
Published in: Journal of Electronic Materials / Issue 3/2024
Print ISSN: 0361-5235
Electronic ISSN: 1543-186X
DOI: https://doi.org/10.1007/s11664-023-10824-w

Springer Professional

Abstract

Please log in to get access to your license.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Other articles of this Issue 3/2024

Investigation of Quaternary BF-0.32PT-0.05BZ-xPNN Piezoelectric Ceramics with High Transduction Coefficient

Microstructural Response of Highly Porous Sintered Nano-silver Particle Die Attachments to Thermomechanical Cycling

The Interfacial Reaction of Ni/In/Ni Sandwich Structure During Solid-State Isothermal Aging

Design and Substrate Material-Based Analysis of a Sriyantra/Srichakra-Shaped Fractal Wideband Monopole Antenna for S-, C-, X-, and Ku-band Communication Applications

Network Structure and Mechanical Properties of Flexible Electronic Interconnects based on Linear Low-Density Polyethylene (LLDPE) and Liquid Silicone Rubber (LSR) Conductive Polymer Composites

Electron–Phonon Coupling and Carrier Relaxation Times in Gallium Antimonide Under Strain