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Journal of Electronic Materials

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04-12-2023 | Original Research Article

Superior Impact Ionization Rate in Deep Gate LDMOS Devices to Improve the Figure of Merit and Lattice Temperature

Authors: Fateme Rezaei, Ali A. Orouji, Abdollah Abbasi

Published in: Journal of Electronic Materials | Issue 3/2024

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Abstract

This paper introduces a deep gate lateral double-diffused MOSFET (LDMOS) structure. The proposed LDMOS is a superior impact ionization rate (SIIR-LDMOS) transistor. The primary focus of our research was to reduce the impact ionization rate and improve key performance metrics. To address this, we implemented a modified drift region and optimized layout design. One key aspect of the proposed structure is the inclusion of an N-type area in the drift region, specifically aimed at decreasing the impact ionization rates. By reducing these rates, we were able to effectively control the electric field and enhance the figure of merit. The results of our study demonstrate improvements in breakdown voltage, on-state resistance, figure of merit, and maximum lattice temperature by approximately 54.88%, 20.8%, 209.15%, and 10.09%, respectively. Importantly, we observed that the lattice temperature in the SIIR-LDMOS structure was lower than in the conventional LDMOS transistor. This further supports the advantages of our proposed design. The enhanced figure of merit and breakdown voltage strongly position the SIIR-LDMOS as a promising candidate for future power MOSFETs.

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Title: Superior Impact Ionization Rate in Deep Gate LDMOS Devices to Improve the Figure of Merit and Lattice Temperature
Authors: Fateme Rezaei
Ali A. Orouji
Abdollah Abbasi
Publication date: 04-12-2023
Publisher: Springer US
Published in: Journal of Electronic Materials / Issue 3/2024
Print ISSN: 0361-5235
Electronic ISSN: 1543-186X
DOI: https://doi.org/10.1007/s11664-023-10824-w

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