Top

Journal of Computational Electronics

Published in:

11-10-2017

3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual-material-gate (DMG) SOI FinFETs

Authors: Rajesh Saha, Srimanta Baishya, Brinda Bhowmick

Published in: Journal of Computational Electronics | Issue 1/2018

Activate our intelligent search to find suitable subject content or patents.

search-config

AI-assisted search

Off

Abstract

Here, we develop a 3D analytical model for potential in a lightly doped dual-material-gate FinFET in the subthreshold region. The model is based on the perimeter-weighted sum of a dual-material double-gate (DMDG) asymmetric MOSFET and a DMDG symmetric MOSFET. The potential model is used to determine the minimum surface potential needed to obtain the threshold voltage \((V_{\mathrm{T}})\) and subthreshold swing (SS) by considering the source barrier changes in the leakiest channel path. The proposed model is capable of reducing the drain-induced barrier lowering (DIBL) as well as the hot carrier effects offered by this device. The impact of control gate ratio and work function difference between the two metal gates on \(V_{\mathrm{T}}\) and SS are also correctly established by the model. All model derivations are validated by comparing the results with technology computer-aided design (TCAD) simulation data.

previous article Circuit modeling of the electro-thermal behavior of nanoscale bulk-FinFETs

next article Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 340 Zeitschriften

aus folgenden Fachgebieten:

Bauwesen + Immobilien
Business IT + Informatik
Finance + Banking
Management + Führung
Marketing + Vertrieb
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Wong, H.S.P.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE. 89(3), 259–287 (2001)CrossRef

Yeo, Y.C., King, T.J., Hu, C.: MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Trans. Electron. Devices 50(4), 1027–1035 (2003)CrossRef

Orouji, A.A., Rahimian, M.: Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism. Curr. Appl. Phys. 12(5), 1366–1371 (2012)CrossRef

Kumar, M.J., Chaudhry, A.: Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans. Electron. Devices 51(4), 569–574 (2004)CrossRef

Pal, A., Sarkar, A.: Analytical study of dual material surrounding gate MOSFET to suppress short-channel effects (SCEs). Eng. Sci. Technol. Int. J. 17, 205–212 (2014)CrossRef

Long, W., Ou, H., Kuo, J.M., Chin, K.K.: Dual-material gate (DMG) field effect transistor. IEEE Trans. Electron. Devices 46(5), 865–870 (1999)CrossRef

Zhou, X.: Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering. IEEE Trans. Electron. Devices 47(1), 113–120 (2000)MathSciNetCrossRef

Tsormpatzoglou, A., Dimitriadis, C.A., Clerc, R., Rafhay, Q., Pananakakis, G., Ghibaudo, G.: Semianalytical modeling of short-channel effects in Si and Ge symmetrical double gate MOSFETs. IEEE Trans. Electron. Devices 54(8), 1943–1951 (2007)CrossRef

Wong, H.S.P., Frank, D.J., Solomon, P.M.: Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length generation. In: International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), pp. 407–410. San Francisco. USA (1998)

10.

Reddy, G.V., Kumar, M.J.: A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation. IEEE Trans. Nanotechnol. 4(2), 260–268 (2005)CrossRef

11.

Saurabh, S., Kumar, M.J.: Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Devices 58(2), 404–41 (2011)CrossRef

12.

Lou, H., et al.: A junctionless nanowire transistor with a dual-material gate. IEEE Trans. Electron. Devices 59(7), 1829–1836 (2012)CrossRef

13.

Bhattacharya, D., Jha, N.K.: FinFETs: from devices to architectures. Adv. Electron. 2014, 1–21 (2014)CrossRef

14.

Mehrad, M., Orouji, A.A.: Partially cylindrical fin field-effect transistor: a novel device for nanoscale applications. IEEE Trans. Device Mater. Reliab. 10(2), 271–275 (2010)CrossRef

15.

Hong, Y., Guo, Y., Yang, H., Yao, J., Zhang, Ji, J.X.: A novel Bulk-FinFET with dual-material gate. In: 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–3 (2014)

16.

Pei, G., Kedzierski, J., Oldiges, P., Ieong, M., Kan, E.C.-C.: FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans. Electron. Devices 49(8), 1411–1419 (2002)CrossRef

17.

Yang, W., Yu, Z., Tian, L.: Scaling theory for FinFETs based on3-D effects investigation. IEEE Trans. Electron. Devices 54(5), 1140–1147 (2007)CrossRef

18.

Ritzenthaler, R., Lime, F., Faynot, O., Cristoloveanu, S., Iñiguez, B.: 3D analytical modelling of subthreshold characteristics in vertical multiple gate FinFET transistors. Solid State Electron. 65, 94–102 (2011)CrossRef

19.

Tsormpatzoglou, A., Dimitriadis, C.A., Clerc, R., Pananakakis, G., Ghibaudo, G.: Semianalytical modeling of short-channel effects in lightly doped silicon trigate MOSFETs. IEEE Trans. Electron. Devices 55(10), 2623–2631 (2008)CrossRef

20.

Rios, R., et al.: Comparison of junctionless and conventional trigate transistors with down to 26 nm. IEEE Electron. Device Lett. 32(9), 1170–1172 (2011)CrossRef

21.

Sentaurus Device User Guide. Synopsys, Inc. (2011)

22.

McKelvey, J.P.: Solid State and Semiconductor Phyisics. Harper and Row publisher, New york (1996)

23.

Tripathi, S., Narendar, V.: A three-dimensional (3D) analytical model for subthreshold characteristics of uniformly doped FinFET. Superlattices Microstruct. 83, 476–487 (2015)CrossRef

24.

Nawaz, S.M., Dutta, S., Chattopadhyay, A., Mallik, A.: Comparison of random dopant and gate-metal workfunction variability between junctionless and conventional FinFETs. IEEE Electron. Device Lett. 35(6), 663–665 (2014)CrossRef

25.

Paul, B.C., Tu, R., Fujita, S., Okajima, M., Lee, T.H., Nishi, Y.: An analytical compact circuit model for nanowire FET. IEEE Trans. Electron. Devices 54(7), 1637–1644 (2007)CrossRef

26.

Kumar, A., Kedzierski, J., Laux, S.E.: Quantum-based simulation analysis of scaling in ultrathin body device structures. IEEE Trans. Electron. Devices 52(4), 614–617 (2005)CrossRef

27.

Colinge, J.P., Alderman, J.C., Xiong, W., Cleavelin, C.R.: Quantum-mechanical effects in trigate SOI MOSFETs. IEEE Trans. Electron. Devices 53(5), 1131–1136 (2006)CrossRef

28.

Tsormpatzoglou, A., Tassis, D.H., Dimitriadis, C.A., Ghibaudo, G., Collaert, N., Pananakakis, G.: Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFET. Solid State Electron. 57, 31–34 (2011)

29.

Young, K.K.: Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans. Electron. Devices 36, 399–402 (1989)CrossRef

30.

Hamid, H.A.E., Guitart, J.R., Iniguez, B.: Two dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs. IEEE Trans. Electron. Devices 54, 1402–1408 (2007)CrossRef

31.

Tsormpatzoglou, A., Dimitriadis, C.A., Clerc, R., Pananakakis, G., Ghibaudo, G.: Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs. IEEE Trans. Electron. Devices 55(9), 2512–2516 (2008)CrossRef

32.

Fasarakis, N., Tsormpatzoglou, A., Tassis, D.H., Dimitriadis, C.A., Papathanasiou, K., Jomaah, J., Ghibaudo, G.: Analytical unified threshold voltage model of short-channel FinFETs and implementation. Solid State Electron. 64, 34–41 (2011)CrossRef

33.

Kumar, P.R., Mahapatra, S.: Analytical Modelling of quantum threshold voltage for triple gate MOSFET. Solid State Electron. 54, 1586–1591 (2010)CrossRef

34.

Subramanian, V., et al.: Impact of fin width on digital and analog performances of n-FinFETs. Solid State Electron. 51, 551–559 (2007)CrossRef

Title: 3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual-material-gate (DMG) SOI FinFETs
Authors: Rajesh Saha
Srimanta Baishya
Brinda Bhowmick
Publication date: 11-10-2017
Publisher: Springer US
Published in: Journal of Computational Electronics / Issue 1/2018
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI: https://doi.org/10.1007/s10825-017-1072-x

Springer Professional

Abstract

Please log in to get access to your license.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Springer Professional "Wirtschaft"

Other articles of this Issue 1/2018

Impact analysis of statistical variability on the accuracy of a propagation delay time compact model in nano-CMOS technology

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

Design and analysis of a gate-all-around CNTFET-based SRAM cell

Single- and dual-band dispersion compensation unit using apodized chirped fiber Bragg grating

Observation of chaotic and strange nonchaotic attractors in a simple multi-scroll system