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Journal of Electronic Testing

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06-12-2020

A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits

Authors: Sayandeep Sanyal, Mayukh Bhattacharya, Amit Patra, Pallab Dasgupta

Published in: Journal of Electronic Testing | Issue 6/2020

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Abstract

Traditional literature on analog testing deals with the propagation of faults to the output ports of a circuit. Often the percentage of detected faults remains low because suitable stimuli cannot be found for propagating certain faults to the outputs. Existing technology supports monitoring internal nets of a circuit, thereby improving fault detection by observing their effect on internal nets. However, this approach is feasible only if the number of internal nets probed by the built-in test structure is limited. This paper presents a structured approach that identifies a small well-chosen subset of internal nets which, when probed, can increase the coverage of analog faults. Further, it describes a formal methodology to identify distinct sub-circuits in a given design, that could be independently probed for detection of faults. Thus, for a given fault universe, the complexity of simulations can be reduced significantly by simulating only the sub-circuits rather than the entire design. We utilize the speed of DC analysis, some common features of analog signals, and partitioning of the transistor netlist using a Channel Connected Graph to accomplish this outcome. We report significant improvement in fault coverage on several circuits including some Analog/Mixed-Signal benchmarks.

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Title: A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits
Authors: Sayandeep Sanyal
Mayukh Bhattacharya
Amit Patra
Pallab Dasgupta
Publication date: 06-12-2020
Publisher: Springer US
Published in: Journal of Electronic Testing / Issue 6/2020
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI: https://doi.org/10.1007/s10836-020-05915-z

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