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Journal of Electronic Testing
Published in: Journal of Electronic Testing 6/2020

21-11-2020

Identification of Logic Paths Influenced by Severe Coupling Capacitances

Authors: I. D. Meza-Ibarra, V. Champac, R. Gomez-Fuentes, J. R. Noriega, A. Vera-Marquina

Published in: Journal of Electronic Testing | Issue 6/2020

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Abstract

Signals in modern integrated circuits travel through complex interconnect structures, which present several layers and important coupling capacitance effects. Even more, the impact of signal coupling on the overall circuit behavior has grown with technology scaling as the interconnect have become taller. In this paper, a methodology to identify those logic paths more significantly influenced by the coupling capacitances is presented. The proposed methodology is based on a modified Dijkstra’s algorithm, which finds those paths between a primary input and a primary output more severely influenced by the coupling capacitances. This methodology can be used to validate circuit behavior and it can also be applied in testing techniques oriented to detect interconnect defects (e.g., opens and short defects). The proposed methodology is applied to ISCAS’85 benchmark circuits to show its feasibility.
previous article A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits
next article Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs

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Literature
1.
Arumi D, Rodriguez-Montanes R, Figueras J (2008) Experimental characterization of cmos interconnect open defects. IEEE Trans Comput-Aided Des Integr Circ Syst 27(1):123–136CrossRef
2.
Bay X, Dey S, Krstic A (2003) Hyac: a hybrid structural sat based atpg for crosstalk. In: International test conference, pp 112–121
3.
Bell J (1996) Timing analysis of logic-level digital circuits using uncertainty intervals. Ph.D. dissertation, Texas A&M University
4.
Bhuvaneswari M (2014) Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems. Springer, BerlinMATH
5.
Chen W, Gupta S K, Breuer MA (1997) Analytic models for crosstalk delay and pulse analysis under non-ideal inputs. In: International test conference. IEEE, pp 809–818
6.
Chen W, Gupta S K, Breuer MA (1998) Test generation in vlsi circuits for crosstalk noise. In: International test conference 1998. Proceedings. IEEE, pp 641–650
7.
Cong J, Pan Z, He L, Koh C -K, Khoo K -Y (1997) Interconnect design for deep submicron ics. In: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design. IEEE Computer Society, pp 478–485
8.
Cormen T H, Leiserson C E, Rivest R L, Stein C (2001) Introduction to algorithms second edition. The Knuth-Morris-Pratt Algorithm
9.
Cormen T H, Leiserson C E, Rivest R L, Clifford S (2009) Introduction to algorithms. MIT Press, Cambridge MassachusettsMATH
10.
Duarte D, Narayanan V, Irwin M J (2002) Impact of technology scaling in the clock system power. In: Proceedings IEEE Computer Society annual symposium on VLSI. New paradigms for VLSI systems design. ISVLSI 2002, pp 59–64
11.
Gandikota R (2009) Crosstalk noise analysis for nano-meter vlsi circuits. Ph.D. dissertation, The University of Michigan
12.
Gómez R, Girón A, Champac V H (2008) A test generation methodology for interconnection opens considering signals at the coupled lines. J Electron Test 24(6):529–538CrossRef
13.
Hashempour H, Kim Y -B, Park N (2002) A test-vector generation methodology for crosstalk noise faults. In: Defect and fault tolerance, pp 40–47
14.
Heydari P, Pedram M (2001) Analysis and reduction of capacitive coupling noise in high-speed vlsi circuits. In: 2001 International conference on in computer design. ICCD 2001. Proceedings. IEEE, pp 104–109
15.
Heydari P, Pedram M (2005) Capacitive coupling noise in high-speed vlsi circuits. IEEE Trans Comput-Aided Des Integr Circ Syst 24(3):478–488CrossRef
16.
Konuk H (1997) Fault simulation of interconnect opens in digital CMOS circuits. In: IEEE international test conference, pp 597–606
17.
Krstic A, Liou J -J, Jiang Y -M, Cheng K -T (2001) Delay testing considering crosstalk-induced effects. In: International test conference, pp 558–567
18.
Li W, Reddy S, Sahni S (1989) On path selection in combinational logic circuits. IEEE Trans Comput-Aided Des Integr Circ Syst 8(1):56–63CrossRef
19.
Li H, Zang Y, Li X (2003) Delay test pattern generation considering crosstalk-induced effects. In: IEEE Asian test symposium, pp 178–183
20.
Lin X, Rajski J (2008) Test generation for interconnect opens. In: international test conference, pp 1–7
21.
Moll F, Rubio A (1992) Spurious Signals In Digital CMOS VLSI circuits: a propagation analysis. IEEE Trans Circ Syst—II Analog Digit Signal Process 39(10):749–752CrossRef
22.
Murakami A, Kajihara S, Sasao T, Pomeranz R, Reddy S M (2000) Selection of potentially testable path delay faults for test generation. In: International test conference, pp 376–384
23.
Nazarian S, Pedram M (2008) Crosstalk-affected delay analysis in nanometer technologies. Int J Electron 95(9):903–937CrossRef
24.
Nazarian S, Huang H, Natarajan S, Gupta S K, Breuer MA (2002) Xiden: crosstalk target identification framework. In: Test conference, 2002 Proceedings. International. IEEE, pp 365–374
25.
Needham W, Prunty C, Yeoh E (1998) High volume microprocessor test escapes, an analysis of defect our test are missing. In: International test conference, pp 25–34
26.
Pandey V, Yadav S, Arora P (2016) Retiming technique for clock period minimization using shortest path algorithm. In: 2016 International conference on computing, communication and automation (ICCCA). IEEE, pp 1418–1423
27.
Qiu W, Walker D (2003) An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit. In: International test conference, pp 593–601
28.
Reddy S, Pomeranz I, Liu C (2008) On tests to detect via opens in digital cmos circuits. In: 45th IEEE design automation conference, pp 840–845
29.
Rubio A, Itazaki N, Xu X, Kinoshita K (1994) An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. IEEE Trans Comput-Aided Des Integr Circ Syst 13(3):387–395CrossRef
30.
Shen P -F, Li H -W, Xu Y -J, Li X -W (2005) Non-robust test generation for crosstalk-induced delay faults. In: Asian test symposium, pp 120–125
31.
Tani S, Teramoto M, Fukazawa M, Matsuhiro K (1998) Efficient path selection for delay testing based on partial path evaluation. In: VLSI test symposium, pp 188–193
32.
Tayade R, Abraham J A (2009) Critical path selection for delay testing considering coupling noise. J Electron Test: Theory Appl 25:213–223CrossRef
33.
Vittal A, Hui Chen L, Marek-Sadowska M, Wang K -P, Yang S (1999) Crosstalk in vlsi interconnections. IEEE Trans Comput-Aided Des Integr Circ Syst 18(12):1817–1824CrossRef
34.
Weiss MA (2012) Data structures & algorithm analysis in C++. Pearson Education
35.
Zenteno A, Champac VH, Figueras J (2001) Detectability conditions of full opens in the interconnections. J Electron Test: Theory Appl 17:85–95CrossRef
36.
Zhao L, Zhao J (2017) Comparison study of three shortest path algorithm. In: 2017 International conference on computer technology, electronics and communication. IEEE, pp 748–751
Metadata
Title
Identification of Logic Paths Influenced by Severe Coupling Capacitances
Authors
I. D. Meza-Ibarra
V. Champac
R. Gomez-Fuentes
J. R. Noriega
A. Vera-Marquina
Publication date
21-11-2020
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 6/2020
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-020-05911-3

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