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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 6/2008

01.12.2008

A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

verfasst von: Roberto Gómez, Alejandro Girón, Victor H. Champac

Erschienen in: Journal of Electronic Testing | Ausgabe 6/2008

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Abstract

Interconnection opens have become important defects in nanometer technologies. The behavior of these defects depends on the structure of the affected devices, the trapped gate charge and the surrounding circuitry. This work proposes an enhanced test generation methodology to improve the detectability of interconnection opens. This test methodology is called OPVEG. OPVEG uses layout information and a commercial stuck-at ATPG. Those signal values at the coupled lines which favor the detection of the opens, under a boolean based test, are attempted to be generated. The methodology is applied to four ISCAS85 benchmark circuits. The results show that a significant number of considered coupled signals are set to proper logic values. Hence, the likelihood of detection of interconnection opens is increased. The results are also given in terms of the amount of coupling capacitance having logic conditions favoring the defect detection. This shows the OPVEG benefits. Furthermore, those lines difficult to test can be identified. This information can be used by the designer to take design for test measures.
Vorheriger Artikel Self-Testing Embedded Borden t-UED Code Checkers for t = 2 k q − 1 with q = 2 m  − 1
Nächster Artikel An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS

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Metadaten
Titel
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
verfasst von
Roberto Gómez
Alejandro Girón
Victor H. Champac
Publikationsdatum
01.12.2008
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 6/2008
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-008-5085-z

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